Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a one-to-one mapping between input and output patterns. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Some quantum signal processing applications like filters and image processing applications require the results of arithmetic operations to be saturated. Saturation occurs when adding two numbers with the same sign and this can be done through a quantum saturating adder. This paper proposed a reversible quantum saturating adder with efficient quantum criteria like quantum cost, number of ancilla, and number of garbage outputs. We firstly propose a reversible n-bit quantum saturation generator block which is applied to a quantum adder and construct a quantum saturating adder circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 18% and 33% improvement in quantum cost and garbage outputs, compared to its counterpart, respectively.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a one-to-one mapping between input and output patterns. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Some quantum signal processing applications like filters and image processing applications require the results of arithmetic operations to be saturated. Saturation occurs when adding two numbers with the same sign and this can be done through a quantum saturating adder. This paper proposed a reversible quantum saturating adder with efficient quantum criteria like quantum cost, number of ancilla, and number of garbage outputs. We firstly propose a reversible n-bit quantum saturation generator block which is applied to a quantum adder and construct a quantum saturating adder circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 18% and 33% improvement in quantum cost and garbage outputs, compared to its counterpart, respectively.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Abstract Reversible logic has become a fundamental paradigm in modern computing, serving as the theoretical basis for quantum computation. Clifford + T gates are used because of their robustness against decoherence faults in quantum circuits. However, the use of T gates introduces implementation challenges due to their relatively high cost. In quantum image processing, saturated arithmetic is essential to ensure that results, such as the sum of two numbers, remain within a strict valid range to prevent overflow. While a few quantum saturating adders exist, this work presents the first fault-tolerant Clifford + T-based saturating generator block. Its key innovation is a constant T-depth and low quantum cost, making it both cascadable and scalable for larger adders. Simulations in the Quirk tool confirm its accuracy, and results demonstrate a 26% T-depth and 13.3% T-count improvements of the proposed addition over current methods. This design applies to NEQR-based quantum image brightness adjustment.
Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.