The comparator as a decision element in RSFQ circuits

Yingyi Shao, Huiwu Wang, Lu Zhang +4 more

Timur V. Filippov, Anubhav Sahu, Dmitri E. Kirichenko +2 more

The Josephson balanced comparator (BC) is a decision-making element and a key building block for all RSFQ logic cells. The comparator is usually characterized by two parameters: gray zone and threshold value. Both parameters depend on the comparator's design, the design of a BC's driver, as well as temperature and frequency of operation. In this paper, we focus on the high-frequency properties of the balanced comparators designed for the Nb SFQ5ee fabrication node at MIT-LL. RSFQ circuits, fabricated at this node, operate nowadays routinely at about 50 GHz. We demonstrate that a further increase of the operational frequency up to 75 GHz with a bit-error rate (BER) of 10-14can be achieved by optimizing the comparator's driver design. We estimate BER of 10-3at 100 GHz, which is not enough for complex circuits. An acceptable BER at 100 GHz requires additional optimization of design and fab.

V. K. Kaplunenko

Taghrid Haddad, Olaf Wetzstein, Sonja Engert +2 more

The Josephson comparator is one of the fundamental building blocks of rapid single flux quantum (RSFQ) electronics. Within this circuit family it is the exclusive device which provides logical data processing. The Josephson comparator is also the basic decision element for very fast analog-to-digital converters and sampler circuits for low input power and high-bandwidth signals based on the RSFQ technique. The performance of those devices is fundamentally determined by the characteristics of the Josephson comparator. In this study the gray zone dependency on the clock frequency of a Josephson comparator is investigated by simulations concerning the influence of thermal noise. This investigation is performed for a series of operating points defined by the bias current and different noise levels defined by the operating temperature. In contrast to former investigations, we analyzed the comparator embedded in a realistic environment for output data processing. We identified a characteristic clock frequency f c for a comparator topology designed for a 1 kA cm − 2 niobium fabrication technology. The gray zone of 8 µA remains constant for clock frequencies below f c = 15 GHz and starts to increase for larger frequencies. We also found out that this characteristic frequency is independent of the intensity of thermal noise and therefore independent of temperature.

Nobuyuki Yoshikawa, 博史 多胡, K. Yoneyama

We will propose a new design approach for single-flux-quantum (SFQ) logic circuits based on a binary decision diagram (BDD). The BDD is a way to represent a logical function by using a directed graph, which is composed of nodes having one input (root) and two outputs (branches). The node has binary states internally which can be controlled from outside, and it switches a messenger entering from the root into one of two branches depending on the internal state. It has been proven that any combinational logic can be represented by this basic element. We will show that the BDD is effectively implemented by an SFQ circuit, where the node is replaced with an SFQ D/sub 2/ flip-flop. Important features of the BDD SFQ logic circuit are simplicity of circuit structure, self-timed nature and high modularity. We have designed a BDD SFQ adder and showed that the junction count and latency are smaller than that of the conventional RSFQ adder.