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IEEE Transactions on Applied Superconductivity

Experimental Evaluation of Josephson Balanced Comparators Toward 100 GHz RSFQ Circuits

Timur V. Filippov, Anubhav Sahu, Dmitri E. Kirichenko, M. Celik, Deepnarayan Gupta

Published Jan 10, 2024• 7 citations
Publisher

Abstract

The Josephson balanced comparator (BC) is a decision-making element and a key building block for all RSFQ logic cells. The comparator is usually characterized by two parameters: gray zone and threshold value. Both parameters depend on the comparator's design, the design of a BC's driver, as well as temperature and frequency of operation. In this paper, we focus on the high-frequency properties of the balanced comparators designed for the Nb SFQ5ee fabrication node at MIT-LL. RSFQ circuits, fabricated at this node, operate nowadays routinely at about 50 GHz. We demonstrate that a further increase of the operational frequency up to 75 GHz with a bit-error rate (BER) of 10-14can be achieved by optimizing the comparator's driver design. We estimate BER of 10-3at 100 GHz, which is not enough for complex circuits. An acceptable BER at 100 GHz requires additional optimization of design and fab.

DOI
10.1109/tasc.2024.3351626

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The Josephson balanced comparator (BC) is a decision-making element and a key building block for all RSFQ logic cells. The comparator is usually characterized by two parameters: gray zone and threshold value. Both parameters depend on the comparator's design, the design of a BC's driver, as well as temperature and frequency of operation. In this paper, we focus on the high-frequency properties of the balanced comparators designed for the Nb SFQ5ee fabrication node at MIT-LL. RSFQ circuits, fabricated at this node, operate nowadays routinely at about 50 GHz. We demonstrate that a further increase of the operational frequency up to 75 GHz with a bit-error rate (BER) of 10-14can be achieved by optimizing the comparator's driver design. We estimate BER of 10-3at 100 GHz, which is not enough for complex circuits. An acceptable BER at 100 GHz requires additional optimization of design and fab.
The balanced comparator, a pair of Josephson junctions, is a key building block and decision-making element for the Rapid Single Flux Quantum (RSFQ) logic cells. The properties of the balanced comparator (BC) define the maximum clock frequency and bit error rate (BER) of RSFQ cells and circuits. Comparators are well characterized by two parameters, the gray zone (GZ) and the gray zone threshold (GZT). Both parameters depend on the dynamic properties of a pair of junctions forming the BC and its surrounding circuitry. In addition, the gray zone depends on the thermal noise in Josephson junctions. The GZ and GZT parameters can be easily measured for various balanced comparators and be used for model-to-hardware correlations. This makes the balanced comparator a unique circuit to validate and calibrate any Josephson simulator by comparing measured and simulated characteristics, including both dynamic and noise properties. In this paper we used a set of balanced comparators designed for the SFQ5ee fabrication process at MIT Lincoln Laboratory to validate and calibrate the Synopsys PrimeSim HSPICE simulator. We were able to match experimental and simulated results and reproduce in simulations the main features observed experimentally and predicted theoretically. A list of recommended design variations to validate a Josephson simulator is provided.
The Josephson balanced comparator (BC) is a key component for all RSFQ/ERSFQ logic cells. Its frequency-dependent properties (gray zone and threshold current value) define the maximum clock frequency and bit error rate (BER) of RSFQ/ERSFQ circuits. The balanced comparator can also be used for various monitoring purposes. In this paper, we focus on clock sources and analyze several of them by means of BCs. We show experimentally how local overheating, associated with sub-optimally designed analog clock sources, can compromise the HF performance of a balanced comparator as well as an RFSQ/ERSFQ circuit on the same chip. We also investigate a clock source based on an external HF generator followed by an on-chip DC/SFQ converter and a frequency doubler. We use the balanced comparator's performance to optimize the on-chip part of the clock source at HF. In addition, we verify the advantage of overshunting the comparator driver to achieve higher clock frequency and lower BER. All test circuits were designed for the SFQ5ee fabrication node at MIT-LL, but conclusions can be applied to other fabrication processes.
The Josephson balanced comparator, a decision-making circuit comprising two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured, is ubiquitous in single flux quantum (SFQ) logic. Its noise properties are crucial for the performance of logic devices. The characteristics of the balanced comparator can also be used to monitor fab process and design implementation as an indicator for excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure gray zone of various comparators fabricated in different nodes of process at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies and an analog testbed to perform high frequency characterization. Experimental results for gray zone of comparators designed for fabrication nodes with different current densities, sheet resistances, critical damping are presented and studied as a function of clock frequency.
The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.
The Josephson comparator is one of the fundamental building blocks of rapid single flux quantum (RSFQ) electronics. Within this circuit family it is the exclusive device which provides logical data processing. The Josephson comparator is also the basic decision element for very fast analog-to-digital converters and sampler circuits for low input power and high-bandwidth signals based on the RSFQ technique. The performance of those devices is fundamentally determined by the characteristics of the Josephson comparator. In this study the gray zone dependency on the clock frequency of a Josephson comparator is investigated by simulations concerning the influence of thermal noise. This investigation is performed for a series of operating points defined by the bias current and different noise levels defined by the operating temperature. In contrast to former investigations, we analyzed the comparator embedded in a realistic environment for output data processing. We identified a characteristic clock frequency f c for a comparator topology designed for a 1 kA cm − 2 niobium fabrication technology. The gray zone of 8 µA remains constant for clock frequencies below f c = 15 GHz and starts to increase for larger frequencies. We also found out that this characteristic frequency is independent of the intensity of thermal noise and therefore independent of temperature.
At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.