Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Nature

Scaling and networking a modular photonic quantum computer

H. Aghaee Rad, T. Ainsworth, Rafael N. Alexander, B. Altieri, Mohsen Falamarzi Askarani, R. Baby, Leonardo Banchi, Ben Q. Baragiola, J. Eli Bourassa, Rachel S. Chadwick, I. Charania, Hongxiang Chen, Matthew J. Collins, Pietro Contu, Nathan D’Arcy, Guillaume Dauphinais, Robbe De Prins, D. Deschenes, Ilaria Di Luch, Sebastián Duque, Parimal Edke, S. E. Fayer, Samuele Ferracin, Hugo Ferretti, José Gefaell, Scott Glancy, Carlos González-Arciniegas, T. Grainge, Z. Han, Jacob Hastrup, L. G. Helt, Timo Hillmann, J. Hundal, S. Izumi, Thomas Jaeken, M. Jonas, Sacha Kocsis, Inna Krasnokutska, Mikkel V. Larsen, P. Laskowski, Fabian Laudenbach, Jonathan Lavoie, M. Li, Emma Lomonte, Carlos E. Lopetegui, Ben Luey, Austin P. Lund, Chensheng Ma, Lars S. Madsen, Dylan H. Mahler, L. Mantilla Calderón, M. Menotti, Filippo M. Miatto, Blair Morrison, Priya J. Nadkarni, Tomohiro Nakamura, Leonhard Neuhaus, Zeyue Niu, R. Noro, K. Papirov, Arthur Chalom Pesah, D. S. Phillips, William N. Plick, T. Rogalsky, Fabien Rortais, Javier Sabines-Chesterking, S. Safavi-Bayat, E. Sazhaev, M. Seymour, Kimia Rezaei Shad, M. Silverman, Srinivasan Ashwyn Srinivasan, M. Stephan, Q. Y. Tang, Joel F. Tasker, Yong Siah Teo, R. B. Then, J. E. Tremblay, Ilan Tzitrin, Varun Vaidya, Michael Vasmer, Z. Vernon, L. F. S. S. M. Villalobos, Blayney W. Walshe, R. Weil, X. Xin, X. Yan, Yuan Yao, M. Zamani Abnili, Yanbing Young Zhang

Published Jan 22, 2025• 184 citations
Publisher

Abstract

Photonics offers a promising platform for quantum computing1–4, owing to the availability of chip integration for mass-manufacturable modules, fibre optics for networking and room-temperature operation of most components. However, experimental demonstrations are needed of complete integrated systems comprising all basic functionalities for universal and fault-tolerant operation5. Here we construct a (sub-performant) scale model of a quantum computer using 35 photonic chips to demonstrate its functionality and feasibility. This combines all the primitive components as discrete, scalable rack-deployed modules networked over fibre-optic interconnects, including 84 squeezers6 and 36 photon-number-resolving detectors furnishing 12 physical qubit modes at each clock cycle. We use this machine, which we name Aurora, to synthesize a cluster state7 entangled across separate chips with 86.4 billion modes, and demonstrate its capability of implementing the foliated distance-2 repetition code with real-time decoding. The key building blocks needed for universality and fault tolerance are demonstrated: heralded synthesis of single-temporal-mode non-Gaussian resource states, real-time multiplexing actuated on photon-number-resolving detection, spatiotemporal cluster-state formation with fibre buffers, and adaptive measurements implemented using chip-integrated homodyne detectors with real-time single-clock-cycle feedforward. We also present a detailed analysis of our architecture’s tolerances for optical loss, which is the dominant and most challenging hurdle to crossing the fault-tolerant threshold. This work lays out the path to cross the fault-tolerant threshold and scale photonic quantum computers to the point of addressing useful applications. A proof-of-principle study reports a complete photonic quantum computer architecture that can, once appropriate component performance is achieved, deliver a universal and fault-tolerant quantum computer.

DOI
10.1038/s41586-024-08406-9

Related papers

Blueprint for a Scalable Photonic Fault-Tolerant Quantum Computer

J. Eli Bourassa, Rafael N. Alexander, Michael Vasmer +10 more

Photonics is the platform of choice to build a modular, easy-to-network quantum computer operating at room temperature. However, no concrete architecture has been presented so far that exploits both the advantages of qubits encoded into states of light and the modern tools for their generation. Here we propose such a design for a scalable fault-tolerant photonic quantum computer informed by the latest developments in theory and technology. Central to our architecture is the generation and manipulation of three-dimensional resource states comprising both bosonic qubits and squeezed vacuum states. The proposal exploits state-of-the-art procedures for the non-deterministic generation of bosonic qubits combined with the strengths of continuous-variable quantum computation, namely the implementation of Clifford gates using easy-to-generate squeezed states. Moreover, the architecture is based on two-dimensional integrated photonic chips used to produce a qubit cluster state in one temporal and two spatial dimensions. By reducing the experimental challenges as compared to existing architectures and by enabling room-temperature quantum computation, our design opens the door to scalable fabrication and operation, which may allow photonics to leap-frog other platforms on the path to a quantum computer with millions of qubits.

arXiv:2010.02905•Quantum•Feb 4, 2021•305 citations

Blueprint for a scalable photonic fault-tolerant quantum computer

J. Eli Bourassa, Rafael N. Alexander, Ben Q. Baragiola +1 more

Photonics is the platform of choice to build a modular, easy-to-network quantum computer operating at room temperature. However, no concrete architecture has been presented so far that exploits both the advantages of qubits encoded into states of light and the modern tools for their generation. Here we propose such a design for a scalable fault-tolerant photonic quantum computer informed by the latest developments in theory and technology. Central to our architecture is the generation and manipulation of three-dimensional resource states comprising both bosonic qubits and squeezed vacuum states. The proposal exploits state-of-the-art procedures for the non-deterministic generation of bosonic qubits combined with the strengths of continuous-variable quantum computation, namely the implementation of Clifford gates using easy-to-generate squeezed states. Moreover, the architecture is based on two-dimensional integrated photonic chips used to produce a qubit cluster state in one temporal and two spatial dimensions. By reducing the experimental challenges as compared to existing architectures and by enabling room-temperature quantum computation, our design opens the door to scalable fabrication and operation, which may allow photonics to leap-frog other platforms on the path to a quantum computer with millions of qubits.

•Nov 2, 2024•222 citations

Photonic Chips for Universal Quantum Computing: Retrospective and Prospective

Wei Wang, Menglong Fang, Hao Yu +7 more

Integrated photonic quantum chips have emerged as a promising platform for realizing fault-tolerant photonic quantum computers. Compared with bulk-optics systems, integrated photonics offer compact device footprints, enhanced programmability, and exceptional stability, attributes that are essential for executing large-scale and computationally demanding quantum tasks. In this review, we provide a comprehensive overview of recent advances in both discrete-variable and continuous-variable universal photonic quantum computation. We survey progress in fault-tolerant architectures and state-of-the-art integrated platforms and highlight the key challenges that must be addressed to scale photonic systems toward full fault tolerance. Finally, we outline future opportunities and research directions aimed at bridging the gap between current proof-of-principle demonstrations and fully scalable quantum microprocessors.

quant-pharXiv:2610.11321•Oct 9, 2026•0 citations

Architectural design for a topological cluster state quantum computer

Simon J. Devitt, Austin G. Fowler, Ashley M. Stephens +4 more

The development of a large scale quantum computer is a highly sought after goal of fundamental research and consequently a highly nontrivial problem. Scalability in quantum information processing is not just a problem of qubit manufacturing and control but it crucially depends on the ability to adapt advanced techniques in quantum information theory, such as error correction, to the experimental restrictions of assembling qubit arrays into the millions. In this paper, we introduce a feasible architectural design for large scale quantum computation in optical systems. We combine the recent developments in topological cluster state computation with the photonic module, a simple chip-based device that can be used as a fundamental building block for a large-scale computer. The integration of the topological cluster model with this comparatively simple operational element addresses many significant issues in scalable computing and leads to a promising modular architecture with complete integration of active error correction, exhibiting high fault-tolerant thresholds.

•Nov 23, 2024•70 citations

A manufacturable platform for photonic quantum computing

PsiQuantum team, Koen Alexander, Avishai Benyamini +97 more

Abstract Although holding great promise for low noise, ease of operation and networking 1 , useful photonic quantum computing has been precluded by the need for beyond-state-of-the-art components, manufactured by the millions 2–6 . Here we introduce a manufacturable platform 7 for quantum computing with photons. We benchmark a set of monolithically integrated silicon-photonics-based modules to generate, manipulate, network and detect heralded photonic qubits, demonstrating dual-rail photonic qubits with 99.98% ± 0.01% state preparation and measurement fidelity, Hong–Ou–Mandel (HOM) quantum interference between independent photon sources with 99.50% ± 0.25% visibility, two-qubit fusion with 99.22% ± 0.12% fidelity and a chip-to-chip qubit interconnect with 99.72% ± 0.04% fidelity, conditional on photon detection and not accounting for loss. We preview a selection of next-generation technologies: low-loss silicon nitride (SiN) waveguides and components to address loss, as well as fabrication-tolerant photon sources, high-efficiency photon-number-resolving detectors (PNRDs), low-loss chip-to-fibre coupling and barium titanate (BTO) electro-optic phase shifters for high-performance fast switching.

Nature•Feb 26, 2025•241 citations

Photonic-Interconnected Quantum Chiplets for Modular and Networked Quantum Computing

Murali Krishna Pasupuleti

Abstract: This study investigates photonic-interconnected quantum chiplets as a modular hardware pathway for scalable and networked quantum computing. The central problem is that monolithic quantum processors face compounding constraints in yield, wiring density, cryogenic routing, interconnect loss, calibration complexity and non-local connectivity. Photonic interconnection offers a technically plausible route to divide a large quantum computer into smaller processors while preserving quantum communication across modules through fibre links, photonic switches, optical transduction or integrated photonic interposers. The paper develops an academically rigorous framework that connects quantum-chiplet architecture, photonic integration, quantum error correction, control latency and manufacturability. It uses secondary real-data anchors from recent public demonstrations and a transparent engineering analysis to evaluate whether modular photonic networking can satisfy requirements for distributed logical qubits, entanglement generation and fault-tolerant operation. Results indicate that photonic chiplets can reduce scaling penalties relative to a monolithic wiring strategy when interconnect loss, feed-forward latency and module yield are jointly optimized. The study concludes that photonic-interconnected chiplets are not a minor packaging improvement but a possible architectural transition comparable to the movement from single-die classical processors to heterogeneous chiplet systems. The strongest contribution is a system-level evaluation model that links physical photonic performance with computer-architecture metrics and identifies the practical thresholds that must be met for Nature-level experimental validation. Keywords quantum computing chips, photonic chiplets, modular quantum computing, quantum interconnects, distributed quantum processors, silicon photonics, quantum networking, fault-tolerant quantum computing, optical interposers, quantum error correction, entanglement routing, wafer-scale quantum manufacturing, cryogenic control, quantum architecture, quantum hardware scalability

International Journal of Academic and Industrial Research Innovations(IJAIRI)•May 24, 2026•0 citations
Photonics offers a promising platform for quantum computing1–4, owing to the availability of chip integration for mass-manufacturable modules, fibre optics for networking and room-temperature operation of most components. However, experimental demonstrations are needed of complete integrated systems comprising all basic functionalities for universal and fault-tolerant operation5. Here we construct a (sub-performant) scale model of a quantum computer using 35 photonic chips to demonstrate its functionality and feasibility. This combines all the primitive components as discrete, scalable rack-deployed modules networked over fibre-optic interconnects, including 84 squeezers6 and 36 photon-number-resolving detectors furnishing 12 physical qubit modes at each clock cycle. We use this machine, which we name Aurora, to synthesize a cluster state7 entangled across separate chips with 86.4 billion modes, and demonstrate its capability of implementing the foliated distance-2 repetition code with real-time decoding. The key building blocks needed for universality and fault tolerance are demonstrated: heralded synthesis of single-temporal-mode non-Gaussian resource states, real-time multiplexing actuated on photon-number-resolving detection, spatiotemporal cluster-state formation with fibre buffers, and adaptive measurements implemented using chip-integrated homodyne detectors with real-time single-clock-cycle feedforward. We also present a detailed analysis of our architecture’s tolerances for optical loss, which is the dominant and most challenging hurdle to crossing the fault-tolerant threshold. This work lays out the path to cross the fault-tolerant threshold and scale photonic quantum computers to the point of addressing useful applications. A proof-of-principle study reports a complete photonic quantum computer architecture that can, once appropriate component performance is achieved, deliver a universal and fault-tolerant quantum computer.
Photonics is the platform of choice to build a modular, easy-to-network quantum computer operating at room temperature. However, no concrete architecture has been presented so far that exploits both the advantages of qubits encoded into states of light and the modern tools for their generation. Here we propose such a design for a scalable fault-tolerant photonic quantum computer informed by the latest developments in theory and technology. Central to our architecture is the generation and manipulation of three-dimensional resource states comprising both bosonic qubits and squeezed vacuum states. The proposal exploits state-of-the-art procedures for the non-deterministic generation of bosonic qubits combined with the strengths of continuous-variable quantum computation, namely the implementation of Clifford gates using easy-to-generate squeezed states. Moreover, the architecture is based on two-dimensional integrated photonic chips used to produce a qubit cluster state in one temporal and two spatial dimensions. By reducing the experimental challenges as compared to existing architectures and by enabling room-temperature quantum computation, our design opens the door to scalable fabrication and operation, which may allow photonics to leap-frog other platforms on the path to a quantum computer with millions of qubits.
Photonics is the platform of choice to build a modular, easy-to-network quantum computer operating at room temperature. However, no concrete architecture has been presented so far that exploits both the advantages of qubits encoded into states of light and the modern tools for their generation. Here we propose such a design for a scalable fault-tolerant photonic quantum computer informed by the latest developments in theory and technology. Central to our architecture is the generation and manipulation of three-dimensional resource states comprising both bosonic qubits and squeezed vacuum states. The proposal exploits state-of-the-art procedures for the non-deterministic generation of bosonic qubits combined with the strengths of continuous-variable quantum computation, namely the implementation of Clifford gates using easy-to-generate squeezed states. Moreover, the architecture is based on two-dimensional integrated photonic chips used to produce a qubit cluster state in one temporal and two spatial dimensions. By reducing the experimental challenges as compared to existing architectures and by enabling room-temperature quantum computation, our design opens the door to scalable fabrication and operation, which may allow photonics to leap-frog other platforms on the path to a quantum computer with millions of qubits.
Integrated photonic quantum chips have emerged as a promising platform for realizing fault-tolerant photonic quantum computers. Compared with bulk-optics systems, integrated photonics offer compact device footprints, enhanced programmability, and exceptional stability, attributes that are essential for executing large-scale and computationally demanding quantum tasks. In this review, we provide a comprehensive overview of recent advances in both discrete-variable and continuous-variable universal photonic quantum computation. We survey progress in fault-tolerant architectures and state-of-the-art integrated platforms and highlight the key challenges that must be addressed to scale photonic systems toward full fault tolerance. Finally, we outline future opportunities and research directions aimed at bridging the gap between current proof-of-principle demonstrations and fully scalable quantum microprocessors.
The development of a large scale quantum computer is a highly sought after goal of fundamental research and consequently a highly nontrivial problem. Scalability in quantum information processing is not just a problem of qubit manufacturing and control but it crucially depends on the ability to adapt advanced techniques in quantum information theory, such as error correction, to the experimental restrictions of assembling qubit arrays into the millions. In this paper, we introduce a feasible architectural design for large scale quantum computation in optical systems. We combine the recent developments in topological cluster state computation with the photonic module, a simple chip-based device that can be used as a fundamental building block for a large-scale computer. The integration of the topological cluster model with this comparatively simple operational element addresses many significant issues in scalable computing and leads to a promising modular architecture with complete integration of active error correction, exhibiting high fault-tolerant thresholds.
Abstract Although holding great promise for low noise, ease of operation and networking 1 , useful photonic quantum computing has been precluded by the need for beyond-state-of-the-art components, manufactured by the millions 2–6 . Here we introduce a manufacturable platform 7 for quantum computing with photons. We benchmark a set of monolithically integrated silicon-photonics-based modules to generate, manipulate, network and detect heralded photonic qubits, demonstrating dual-rail photonic qubits with 99.98% ± 0.01% state preparation and measurement fidelity, Hong–Ou–Mandel (HOM) quantum interference between independent photon sources with 99.50% ± 0.25% visibility, two-qubit fusion with 99.22% ± 0.12% fidelity and a chip-to-chip qubit interconnect with 99.72% ± 0.04% fidelity, conditional on photon detection and not accounting for loss. We preview a selection of next-generation technologies: low-loss silicon nitride (SiN) waveguides and components to address loss, as well as fabrication-tolerant photon sources, high-efficiency photon-number-resolving detectors (PNRDs), low-loss chip-to-fibre coupling and barium titanate (BTO) electro-optic phase shifters for high-performance fast switching.
Abstract: This study investigates photonic-interconnected quantum chiplets as a modular hardware pathway for scalable and networked quantum computing. The central problem is that monolithic quantum processors face compounding constraints in yield, wiring density, cryogenic routing, interconnect loss, calibration complexity and non-local connectivity. Photonic interconnection offers a technically plausible route to divide a large quantum computer into smaller processors while preserving quantum communication across modules through fibre links, photonic switches, optical transduction or integrated photonic interposers. The paper develops an academically rigorous framework that connects quantum-chiplet architecture, photonic integration, quantum error correction, control latency and manufacturability. It uses secondary real-data anchors from recent public demonstrations and a transparent engineering analysis to evaluate whether modular photonic networking can satisfy requirements for distributed logical qubits, entanglement generation and fault-tolerant operation. Results indicate that photonic chiplets can reduce scaling penalties relative to a monolithic wiring strategy when interconnect loss, feed-forward latency and module yield are jointly optimized. The study concludes that photonic-interconnected chiplets are not a minor packaging improvement but a possible architectural transition comparable to the movement from single-die classical processors to heterogeneous chiplet systems. The strongest contribution is a system-level evaluation model that links physical photonic performance with computer-architecture metrics and identifies the practical thresholds that must be met for Nature-level experimental validation. Keywords quantum computing chips, photonic chiplets, modular quantum computing, quantum interconnects, distributed quantum processors, silicon photonics, quantum networking, fault-tolerant quantum computing, optical interposers, quantum error correction, entanglement routing, wafer-scale quantum manufacturing, cryogenic control, quantum architecture, quantum hardware scalability