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International Conference on Communication, Image and Signal Processing (CCISP)

Efficient FPGA Implementation of Syndrome-Assisted Layered Belief Propagation Decoder for CV-QKD Systems

Yong Chen, Xueqin Jiang, Genlong Chen, Peng Huang, Enjian Bai, Han Hai

Published Nov 13, 2024• 2 citations
Publisher

Abstract

In this paper, we propose a QC-LDPC decoder architecture with low complexity as well as excellent decoding performance in CV-QKD systems, which employs the syndrome-assisted layered belief propagation decoding algorithm. To minimize the complexity of hardware implementation and resource consumption in iterative decoding, we use fixed-point numbers instead of floating-point numbers to update node messages. Additionally, two-segment nonuniform lookup tables are employed to implement$\psi(x)$efficiently. Besides, the layered syndrome-assisted early termination (LS-ET) scheme is introduced, resulting in the reduction of the number of decoding iterations while maintaining superior frame error rate (FER) performance. The experimental results indicate that the QC-LDPC decoder implemented on an FPGA is capable of achieving throughput of 50.8 Mbps when the code length is 26112 and code rate is 22/68.

DOI
10.1109/ccisp63826.2024.10765534

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In this paper, we propose a QC-LDPC decoder architecture with low complexity as well as excellent decoding performance in CV-QKD systems, which employs the syndrome-assisted layered belief propagation decoding algorithm. To minimize the complexity of hardware implementation and resource consumption in iterative decoding, we use fixed-point numbers instead of floating-point numbers to update node messages. Additionally, two-segment nonuniform lookup tables are employed to implementψ(x)\psi(x)ψ(x)efficiently. Besides, the layered syndrome-assisted early termination (LS-ET) scheme is introduced, resulting in the reduction of the number of decoding iterations while maintaining superior frame error rate (FER) performance. The experimental results indicate that the QC-LDPC decoder implemented on an FPGA is capable of achieving throughput of 50.8 Mbps when the code length is 26112 and code rate is 22/68.
In continuous variable quantum key distribution (CV-QKD) systems, low-density parity check (LDPC) decoders have gained widespread adoption due to their robust error correction capabilities and good adaptability to parallel processing hardware designs. We introduce a syndrome-based normalized min-sum algorithm (S-NMSA) and implement the decoder on FPGAs for high throughput and minimal resource consumption. The decoder utilizes a semi-parallel architecture. The proposed rapid cyclic shifter (RCS) can complete the shift of any dimension matrix in one clock cycle and realizes a significant reduction in hardware resource consumption. The semi-parallel decoding structure attains a 68.5 Mbps processing throughput on the condition that the system clock of the quasi-cyclic (QC) LDPC decoder is 250 Mhz.
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This paper addresses the high-throughput requirements of information reconciliation in continuous-variable quantum key distribution (CV-QKD) systems by proposing an FPGA-based quasi-cyclic low-density parity-check (QC-LDPC) decoder implementation utilizing cross-layer scheduling. Through a preprocessing approach involving base matrix row reordering and data merging, the scheme effectively resolves memory access conflicts in layered decoding, enabling conflict-free parallel processing. Operating at 250 MHz, the decoder achieves a throughput of 100.5 Mbps, representing a 20% improvement over conventional approaches while maintaining equivalent frame error rate performance.
The throughput of error correction is the main bottleneck of continuous variable quantum key distribution (CV-QKD) postprocessing. Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA with limited precision can improve the decoding throughput significantly. However, the limited precision on FPGA results in the existence of residual error-bits after decoding, which lowers the secret key rate and restricts the application of high-rate real-time CVQKD system. In this paper, an efficient decoding scheme is proposed to erase the residual error-bits and decrease the frame errors rate (FER), where the decoding process into two stages and some values of initial Log Likelihood Ratio (LLR) are adjusted according to the proposed principles before starting the second-stage decoding. For the rates 0.2 and 0.1 LDPC codes, numerical results demonstrate that the proposed decoding scheme decreases the FER obviously and the throughputs of 152.47Mbps and 88.32Mbps are achieved, which can be applied to support high-speed CV-QKD system under transmission distance of 25km and 50km respectively.
Abstract This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numerical methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and throughput trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8 ×\times× × improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24 ×\times× × improvement in throughput over a baseline serial decoder.
Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of Eb/N0E_b/N_0Eb​/N0​ Eb/N0 until the BER of 1e−6.