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IEEE International Conference on Quantum Computing and Engineering (QCE)

Low-Power Half-Flux-Quantum based Counter Circuits for Cryogenic Quantum Computers

Yuki Matsumoto, Teruo Tanimoto, Masamitsu Tanaka, Takatsugu Ono

Published Sep 15, 2024• 4 citations
Publisher

Abstract

The number of bits in quantum computers needs to be increased since large problems must be solved to achieve quantum acceleration. Superconducting qubits are the most advanced qubit devices currently available. A method has been proposed to place a quantum-classical interface on a 4 K stage to ensure scalability. The practical implications of a simple counter circuit in the interface and its role in processing the qubit read results have been demonstrated. A method is needed for configuring a counter circuit with low power consumption to improve scalability. In this paper, we design a novel counter circuit using the Half-Flux Quantum (HFQ) technology. This technology operates in cryogenic environments and has lower power consumption than the Single-Flux Quantum (SFQ) tech-nology. In addition, we conducted a comparative evaluation of circuits dedicated to the NISQ algorithm using SFQ and equivalent circuits implemented using HFQ. Assuming the same power consumption technology applicable to SFQ can be applied to HFQ, we found that the proposed HFQ-based counter circuit can reduce the power consumption by up to 97%.

DOI
10.1109/qce60285.2024.00120

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The number of bits in quantum computers needs to be increased since large problems must be solved to achieve quantum acceleration. Superconducting qubits are the most advanced qubit devices currently available. A method has been proposed to place a quantum-classical interface on a 4 K stage to ensure scalability. The practical implications of a simple counter circuit in the interface and its role in processing the qubit read results have been demonstrated. A method is needed for configuring a counter circuit with low power consumption to improve scalability. In this paper, we design a novel counter circuit using the Half-Flux Quantum (HFQ) technology. This technology operates in cryogenic environments and has lower power consumption than the Single-Flux Quantum (SFQ) tech-nology. In addition, we conducted a comparative evaluation of circuits dedicated to the NISQ algorithm using SFQ and equivalent circuits implemented using HFQ. Assuming the same power consumption technology applicable to SFQ can be applied to HFQ, we found that the proposed HFQ-based counter circuit can reduce the power consumption by up to 97%.
The digital circuits in a superconducting quantum computer must be cooled to cryogenic temperatures in a dilution refrigerator for control and information readout of the qubit information. Because the dilution refrigerator's heat capacity is limited, extremely low-power digital circuits are required. Single-flux-quantum (SFQ) circuits and Josephson photomultipliers (JPMs) are expected to serve as control and readout circuits for superconducting quantum computers. These circuits generate minimal heat, but further reductions in power consumption are required to make it possible to build larger, more scalable faulttolerant quantum computers (FTQC). In this paper, we propose a low-power and reliable peripheral circuit for JPM-based qubit readout utilizing an SFQ counter circuit. The counter performs majority voting across repeated readouts, significantly improving the reliability of the JPM readout process. Additionally, we quantitatively evaluate switching errors in SFQ circuits using Josephson junctions with low-critical current values. By integrating these circuit techniques and simulation results, we find that the proposed approach achieves a 90% reduction in power consumption while effectively suppressing the increase in readout error.
Abstract Half-flux-quantum (HFQ) circuits are based on 0–π superconducting quantum interference devices (SQUIDs) and is one of the energy-efficient superconductor digital circuits. The bit energy is determined by the critical current I cn of 0–π SQUID, which can be easily tuned with the loop inductance and junction critical current. In this work, an alternative π–π–π SQUID is adopted to demonstrate HFQ circuits to simplify the fabrication process and enhance circuit energy efficiency. The properties of superconductor/ferromagnet/insulator/superconductor Josephson junctions (π-JJs) are measured with temperature dependence from 4.2 K down to 10 mK. HFQ toggle flip-flops (TFFs) are successfully demonstrated at frequencies of up to 6.7 GHz and 44.5 GHz at temperatures of 4.2 K and 10 mK, respectively. Comparing the HFQ TFF with its rapid single-flux quantum counterpart under the same fabrication process, it is anticipated that the HFQ TFF will exhibit approximately 70% reduction in both static and dynamic energy dissipation. This research establishes the foundation for developing cryogenic interface control and readout circuits for large-scale quantum computing in the future.
We report on low-power operation of the half-flux-quantum (HFQ) shift-register circuit. We used a superconducting quantum interference device composed of two conventional switching junctions (0-junctions) and one π-shifted non-switching magnetic Josephson junction (π-junction) as a switching element, called 0-0-π SQUID. Because the π-shift assists switching by inducing a spontaneous current, the 0-0-π SQUID shows a nominal small critical current value and is easily switched by a weak driving force. This feature allows us to significantly reduce static and dynamic power consumption at junctions and bias-feeding resistors. We carefully designed the HFQ circuit elements using a circuit parameter optimization tool and introducing additional non-switching 0-0-π SQUIDs to compensate for superconductor phase shifts. We fabricated the test circuit of the 4-bit shift-register by forming Nb/PdNi/Nb π-junctions on the Nb four-layer, 10-kA/cm2 device. We successfully obtained correct operation with measured power consumption of 0.12-0.18 μW/bit, which was about 1/10 of the conventional single-flux-quantum shift-register designed with the 0-junctions of the same critical currents and the standard bias voltage.
Cryogenic quantum computers play a leading role in demonstrating quantum advantage. Given the severe constraints on the cooling capacity in cryogenic environments, thermal design is crucial for the scalability of these computers. The sources of heat dissipation include passive inflow via intertemperature wires and the power consumption of components located in the cryostat, such as wire amplifiers and quantum–classical interfaces. Thus, a critical challenge is to reduce the number of wires by reducing the required intertemperature bandwidth while maintaining minimal additional power consumption in the cryostat. One solution to address this challenge is near-data processing using ultralow-power computational logic within the cryostat. Based on the workload analysis and domain-specific system design focused on variational quantum algorithms (VQAs), we propose the cryogenic counter-based coprocessor for VQAs (C3-VQA) to enhance the design scalability of cryogenic quantum computers under the thermal constraint. The C3-VQA utilizes single-flux-quantum logic, which is an ultralow-power superconducting digital circuit that operates at the 4 K environment. The C3-VQA precomputes a part of the expectation value calculations for VQAs and buffers intermediate values using simple bit operation units and counters in the cryostat, thereby reducing the required intertemperature bandwidth with small additional power consumption. Consequently, the C3-VQA reduces the number of wires, leading to a reduction in the total heat dissipation in the cryostat. Our evaluation shows that the C3-VQA reduces the total heat dissipation at the 4 K stage by 30% and 81% under sequential-shot and parallel-shot execution scenarios, respectively. Furthermore, a case study in quantum chemistry shows that the C3-VQA reduces total heat dissipation by 87% with a 10 000-qubit system.
Abstract The use of high-frequency input signals from room-temperature microwave sources makes it difficult to scale up the number of quantum bits in universal quantum computers. To address this issue, superconducting single flux quantum (SFQ) integrated circuits are being explored as suitable candidates for qubit manipulation in universal quantum computers. This paper deals with a scalable SFQ qubit control circuit (SQCC) structure that requires only low-frequency input. The circuit mainly consists of a pulse generator and a counter, that output the SFQ pulse train with adjustable frequency and a controllable number of pulses, which is applicable to control single-qubit Clifford operations. The design of low-voltage rapid single flux quantum (LV-RSFQ) and energy-efficient rapid single flux quantum (ERSFQ) for the SQCC achieves low power consumption and provides a basis for scaling up SQCC to control more qubits. The proposed circuits are fabricated under the SIMIT-Nb03 process and successfully pass test verification. The achieved test results reveal that the adjustable output frequency ranges of the SQCC based on the LV-RSFQ and ERSFQ designs in order are [2.40, 8.11] GHz and [4.81, 5.14] GHz. In the operating frequency range, the circuit is able to generate the correct number of SFQ pulses under control. The controllable number range is from 1 to 128. When the circuits operate at 5 GHz, the total power consumptions of the above circuits in order are 23.88 μW and 6.2 μW. All input signals are low-frequency signals, which frees the control of large-scale qubits from limitations caused by high-frequency inputs produced by room-temperature microwave sources.
A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.