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Computer Science

A Physical Model of Quantum Bit Behavior Based on a Programmable FPGA Integrated Circuit

Jacek Długopolski, Marcin Sadowski, Wawrzyniec Suleja

Published Dec 30, 2024• 0 citations
Publisher

Abstract

The rapidly developing field of quantum computing and the ongoing lack of widely available quantum computers create the need for scientists to build their simulators. However, mathematical simulation of such circuits usually ignores many aspects and problems found in real quantum systems. In this article, the authors describe a quantum bit emulator based on FPGA integrated circuits. In this case, FPGA technology provides real-time massive parallelism of the modeled physical phenomena. The modeled QUBIT is represented using a Bloch sphere. Its quantum state is set and modified only by precise pulses of an electrical signal, and with the help of similar pulses, it manifests its current state in real time. The constructed QUBIT was additionally equipped with decoherence mechanisms and with circuits that intentionally respond to internal and external noises that distort its current quantum state. This article presents and discusses how such a physically built emulator works.

DOI
10.7494/csci.2024.25.4.6289

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The rapidly developing field of quantum computing and the ongoing lack of widely available quantum computers create the need for scientists to build their simulators. However, mathematical simulation of such circuits usually ignores many aspects and problems found in real quantum systems. In this article, the authors describe a quantum bit emulator based on FPGA integrated circuits. In this case, FPGA technology provides real-time massive parallelism of the modeled physical phenomena. The modeled QUBIT is represented using a Bloch sphere. Its quantum state is set and modified only by precise pulses of an electrical signal, and with the help of similar pulses, it manifests its current state in real time. The constructed QUBIT was additionally equipped with decoherence mechanisms and with circuits that intentionally respond to internal and external noises that distort its current quantum state. This article presents and discusses how such a physically built emulator works.
The rapidly developing field of quantum computing and the ongoing lack of widely available quantum computers create the need for scientists to build their simulators. However, mathematical simulation of such circuits usually ignores many aspects and problems found in real quantum systems. In this article, the authors describe a quantum bit emulator based on FPGA integrated circuits. In this case, FPGA technology provides real-time massive parallelism of the modeled physical phenomena. The modeled QUBIT is represented using a Bloch sphere. Its quantum state is set and modified only by precise pulses of an electrical signal, and with the help of similar pulses, it manifests its current state in real time. The constructed QUBIT was additionally equipped with decoherence mechanisms and with circuits that intentionally respond to internal and external noises that distort its current quantum state. This article presents and discusses how such a physically built emulator works.
It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.
The quantum computing represents a new field, which is still being researched, that may have numerous applications in the computer arithmetic, in the encryption - decryption systems, rapid search algorithms and physical systems' emulations. The hardware device that can make this type of calculations is still expensive nowadays and the number of the manufacturers is reduced. On the other hand, the simulation of a quantum computer using the devices currently available on the market - like the FPGA digital circuits - helps in getting an overview of the possibilities that the quantum calculations can provide and it can also be used when simulating physical processes in general. The aim of this article is to present our own solution of an emulator for the quantum calculations using the digital modules implemented in FPGA.
While physical realization of practical large-scale quantum computers is still ongoing, theoretical research of quantum computing applications is facilitated on classical computing platforms through simulation and emulation methods. Nevertheless, the exponential increase in resource requirement with the increase in the number of qubits is an inherent issue in classical modeling of quantum systems. In the effort to alleviate the critical scalability issue in existing FPGA emulation works, a novel FPGA-based quantum circuit emulation framework based on Heisenberg representation is proposed in this paper. Unlike previous works that are restricted to the emulations of quantum circuits of small qubit sizes, the proposed FPGA emulation framework can scale-up to 120-qubit on Altera Stratix IV FPGA for the stabilizer circuit case study while providing notable speed-up over the equivalent simulation model.
As current trend of miniaturization in computing technology continues, modern computing devices would start to exhibit the behaviour of nanoscopic quantum objects. Quantum computing, which is based on the principles of quantum mechanics, becomes a promising candidate for future generation computing system. However, modelling quantum computing systems on existing classical computing platforms before the realization of viable large-scale quantum computer remains a major challenge. The exploration on the modelling of quantum computing systems on field programmable gate array (FPGA) platform, which offers the potential of massive parallelism and allows computational optimization at register-transfer level, is crucial. Due to the exponential growth of resource utilization with the increase in the number of quantum bits (qubit), existing works on modelling of quantum systems on FPGA platform are restricted to simple case studies using small qubit sizes. This work explores the modelling of quantum computing for emulation on FPGA platform based on two types of data structure: (a) state vector model and (b) Heisenberg model. For the conventional state vector modelling approach, an efficient datapath design that is based on serial-parallel hardware architecture, which allows resource sharing between unitary transformations, is proposed. Heisenberg model has been proven to be efficient in modelling stabilizer circuits, which are critical in error correction operations. In the effort to include the consideration of vital quantum error correction in practical quantum systems, a novel FPGA emulation framework that is based on the Heisenberg model is proposed. Effective algorithms for accurate global phase maintenance are proposed to facilitate the modelling of quantum systems based on the Heisenberg representation. The feasibility of the proposed state vector and Heisenberg emulation models are demonstrated based on a number of case studies with different characteristics, which include quantum Fourier transform, Grover’s search algorithm, and stabilizer circuits. Based on the state vector approach, this work has demonstrated the advantage of FPGA emulation over software simulation where hardware emulation of 7-qubit Grover’s search is about 3 × 104 times faster than the software simulation performed on Intel Core i7-4790 processor running at 3.6GHz clock rate. In contrast to the 8-qubit implementation based on the state vector model, the proposed FPGA emulation framework based on the Heisenberg model has successfully modelled 120-qubit stabilizer circuits on the Altera Stratix IV FPGA. In summary, the proposed work in this thesis contributes to the formulation of a proof-of-concept of efficient FPGA emulation framework based on the state vector and Heisenberg models.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.