Building on previous research on frequency allocation optimization for superconducting circuit quantum processors, this work incorporates several techniques to improve overall solution quality. We introduce constraints and imposed edgewise differences help to improve the optimization results. We also introduce optimization variables for the orientation of each edge, defined as the direction from the control qubit to the target qubit, to be chosen during optimization. To scale up to larger processors, multimodule designs are employed with various boundary conditions, thereby enhancing the collective yield. These enhancements allow for greater flexibility in processor design by eliminating the need for handpicked orientations. We support the efficient assembly of large processors with dense connectivity by choosing the best boundary conditions. Examples demonstrate that, at low computational cost, this optimization approach finds a frequency configuration for a square chip with over 1000 qubits and over 10% yield at much larger dispersion levels than required by previous approaches.
Tunable couplers have enabled two-qubit gate fidelities in superconducting quantum processors to approach
99.9%, yet simultaneously suppressing residual interactions and maintaining flexible qubit-frequency allocation remain central challenges for scaling. Here, we propose a double-resonator coupler (DRC) consisting of two resonators interconnected by a single Josephson junction and a capacitor. The hybridized resonator modes provide two mediated exchange paths whose interference controls the qubit-qubit interaction. The DRC enables complete cancellation of residual
ZZ interaction for qubit-qubit detunings well outside the straddling regime, even without direct inter-qubit capacitance, thereby relaxing constraints on frequency allocation and qubit placement. Away from the idle point, the same circuit provides a strong
ZZ interaction of approximately
70MHz, enabling a
20ns controlled-Z gate with simulated coherent infidelity below
10−5. These results establish the DRC as a flexible single-junction coupler architecture for high-fidelity superconducting quantum processors.
Fixed-frequency superconducting quantum processors are one of the most mature quantum computing architectures with high-coherence qubits and simple controls. However, high-fidelity multiqubit gates pose tight requirements on individual qubit frequencies in these processors, and these constraints are difficult to satisfy when constructing larger processors due to the large dispersion in the fabrication of Josephson junctions. In this paper, we propose a mixed-integer-programming-based optimization approach that determines qubit frequencies to maximize the fabrication yield of quantum processors. We study traditional qubit and qutrit (three-level) architectures with cross-resonance interaction processors. We compare these architectures to a differential ac-Stark shift based on entanglement gates and show that our approach greatly improves the fabrication yield and also increases the scalability of these devices. Our approach is general and can be adapted to problems where one must avoid specific frequency collisions.