Recent achievements in the physical size of quantum computers based on superconducting qubits foresee reaching the next milestones of the exponentially growing number of qubits. The promises in the scalability present opportunities in integrated control electronics operating at 4K stage in the dilution refrigerator. In addition to the number of physical qubits, however, commercialization necessitates a further increase in the number of consecutive high-fidelity gate operations within a coherence time of
∼100μs. It leads to the stringent requirement on the duration of qubit-driving microwave pulse
(i.e., <20ns). The microwave pulses should only drive
∣0⟩↔∣1⟩for single qubit gate operations while avoiding leakage to
∣1⟩↔∣2⟩which is the major factor that degrades the gate fidelity. The frequency for
∣1⟩↔∣2⟩,ω12, is typically lower than the frequency for
∣0⟩↔∣1⟩,ω01, by
2π×(160MHz−to−360MHz). The frequency difference
(ω01−ω12), called anharmonicity, is an individual qubit characteristic and becomes the margin for spectral management. But, a short driving pulse even with Gaussian, sine, or raised-cosine shapes eventually widens the spectral width. It would range a few hundred MHz and result in a considerable spectral leakage at
ω12. To mitigate this spectral leakage, the derivative removal by adiabatic gate (DRAG) has been adopted in the pulse shaping [1], [2]. As shown in Fig. 34.4.1, the first-order DRAG pulse shaping is realized by adding two parts as \begin{equation*}\mathsf{O}(\mathrm{t})=\mathsf{S}_{\mathsf{M}}(\mathsf{t})\cdot\mathsf{cos}(\omega_{01}\mathsf{t}+\varphi)+\mathsf{q}_{\mathsf{scale}}\mathsf{S}_{\mathsf{M}}(\mathsf{t})^{\prime}\cdot\mathsf{sin}(\omega_{01}\mathsf{t}+\varphi)\end{equation*} where
SM(t)is the main pulse shape and
qscaleis a coefficient inversely proportional to the anharmonicity. This first-order DRAG makes an asymmetrical spectrum that lowers the left frequency side and raises the right frequency side. Since the
ω12is always on the left side of
ω01, the DRAG can effectively minimize the leakage.
This article presents a cryo-CMOS quantum controller IC for superconducting qubits. The proposed globally synchronized clock system internally generates different local oscillator (LO) frequencies using multiple phase-locked loops (PLLs) driven by a common reference clock. It provides flexibility in spectral management as well as scalability for expansion to a large-scale quantum controller. The test chip includes two PLLs, four pulse modulator channels, and two receiver channels. Implemented chip in 40-nm CMOS shows full functionalities at 3.5 K. The designed pulse modulator circuits are verified with the specifications for expected fidelity of 99.99%.
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.
Scaling superconducting quantum computers toward thousands of control channels remains a difficult hardware problem. This requires reducing room-temperature-to-cryogenic interconnects and 4 K power while retaining channel-specific programmability. We develop a hybrid photonic/CMOS control architecture in which optical fibers distribute shared Gaussian and derivative pulse templates, while local cryogenic CMOS circuits provide event-rate amplitude programming, pulse blocking, hold-duration control, photodetection, and microwave upconversion. The architecture supports template-based XY/DRAG control and smooth-edged flat-top envelopes for two-qubit control through separate local signal paths. Compared with full-waveform Cryo-CMOS, it moves high-speed sampled-waveform generation out of each cryogenic channel. Compared with per-channel photonic waveform delivery, it retains a programmable endpoint after optical distribution for applying updated channel coefficients and control states. We evaluate the architecture using post-layout circuit simulations, optical and interconnect models, and system-level power scaling under a common 4 K output boundary. The modeled downlink power is below 1 mW per qubit-control channel at the thousand-channel scale, substantially below the normalized full-waveform Cryo-CMOS result and in the same range as the strict 50-ohm direct-detection WDM reference. Simulated I- and Q-path outputs are propagated through a five-level transmon model, while the simulated sample-and-hold output is evaluated in a coupled-transmon model. The tested single-qubit cases remain below the 10^-3 worst-state error reference, and the representative two-qubit result remains near the same scale after model-level calibration. These results support low-power photonic delivery with limited in-fridge programmability for template-compatible superconducting-qubit control.
A universal fault-tolerant quantum computer will require large-scale control systems that can realize all the waveforms required to implement a gateset that is universal for quantum computing. Optimization of such a system, which must be precise and extensible, is an open research challenge. Here, we present a cryogenic quantum control integrated circuit (IC) that is able to control all the necessary degrees of freedom of a two-qubit subcircuit of a superconducting quantum processor. Specifically, the IC contains a pair of 4–8-GHz RF pulse generators for
XYcontrol, three baseband current generators for qubit and coupler frequency control, and a digital controller that includes a sequencer for gate sequence playback. After motivating the architecture, we describe the circuit-level implementation details and present experimental results. Using standard benchmarking techniques, we show that the cryogenic CMOS (cryo-CMOS) IC is able to execute the components of a gateset that is universal for quantum computing while achieving single-qubit
XYand
Zaverage gate error rates of 0.17%–0.36% and 0.14%–0.17%, respectively, as well as two-qubit average cross-entropy benchmarking (XEB) cycle error rates of 1.2%. These error rates, which were achieved while dissipating just 4 mW/qubit, are comparable to the measured error rates obtained using baseline room-temperature electronics.