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International Conference on Circuits, Control, Communication and Computing (I4C)

Concatenated Polar and Non binary LDPC codes for High Reliability in Optical Communication System

Saiith Sethu P, Sam Solomon

Published Oct 4, 2024• 1 citation
Publisher

Abstract

Next-generation high-speed optical transport systems require powerful forward error correction (FEC) codes with high error-correcting capabilities to ensure high data reliability. Low density parity check (LDPC) codes are strong candidates for ensuring the high data reliability needed to support data rates of 100 Gb/s, demanded by optical systems. Non-binary LDPC (NB-LDPC) codes provides better performance compared to binary version, as they offer larger coding gains with shorter code lengths and reduced system latency. Despite their advantages, LDPC codes suffer from error floor problem at low bit error rates (BER), with NB-LDPC codes showing error floors at BER around 10-7. High-speed optical transport systems generally require BERs of the order of 10-12. The error floor problem can be mitigated by concatenating LDPC codes with a shorter outer code. Existing works mainly focus on employing Reed Solomon (RS) codes to remove error floor. However, the decoding complexity is high for these codes. This paper proposes concatenated Polar and NB-LDPC codes to address the error floor issue, since polar codes have relatively low encoding and decoding complexity. The channel noise in optical communication systems using optical amplifiers cannot be analyzed using simplified additive white Gaussian noise (AWGN). Hence the channel noise is mathematically derived and proved that chi-square channel model is appropriate than AWGN. Simulation results demonstrate that the proposed concatenated codes over proposed channel model can achieve a net coding gain of around 1.5dB at a BER of 10-12.

DOI
10.1109/i4c62240.2024.10748489

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Next-generation high-speed optical transport systems require powerful forward error correction (FEC) codes with high error-correcting capabilities to ensure high data reliability. Low density parity check (LDPC) codes are strong candidates for ensuring the high data reliability needed to support data rates of 100 Gb/s, demanded by optical systems. Non-binary LDPC (NB-LDPC) codes provides better performance compared to binary version, as they offer larger coding gains with shorter code lengths and reduced system latency. Despite their advantages, LDPC codes suffer from error floor problem at low bit error rates (BER), with NB-LDPC codes showing error floors at BER around 10-7. High-speed optical transport systems generally require BERs of the order of 10-12. The error floor problem can be mitigated by concatenating LDPC codes with a shorter outer code. Existing works mainly focus on employing Reed Solomon (RS) codes to remove error floor. However, the decoding complexity is high for these codes. This paper proposes concatenated Polar and NB-LDPC codes to address the error floor issue, since polar codes have relatively low encoding and decoding complexity. The channel noise in optical communication systems using optical amplifiers cannot be analyzed using simplified additive white Gaussian noise (AWGN). Hence the channel noise is mathematically derived and proved that chi-square channel model is appropriate than AWGN. Simulation results demonstrate that the proposed concatenated codes over proposed channel model can achieve a net coding gain of around 1.5dB at a BER of 10-12.
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Low-density parity-check code (LDPC) not only has good performance approaching the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hot-spot in the field of channel coding in recent years and has a wide range of application prospects in optical communication systems. In this paper, the decoding aspects and performance of LDPC codes are analyzed and compared according to the bit error rate (BER) of LDPC codes. The computer simulation was carried out under additive white Gaussian noise (AWGN) channel and binary phase shift keying (BPSK) modulation. Through theoretical analysis and simulation results, this paper explores the way of multi-rate LDPC decoding.
Error correcting codes are used in virtually all communication systems to ensure reliable transmission of information. In 1948, Shannon established an upper-bound on the maximum rate at which information can be transmitted reliably over a noisy channel. Reliably transmitting information with a rate close to this theoretical limit, known as the channel capacity, has been the goal of channel coding scientists for the last five decades. The rediscovery of low-density parity-check (LDPC) codes in the 1990s added much-renewed excitement in the coding community. LDPC codes are interesting because they can approach channel capacity under sub-optimum decoding algorithms whose complexity is linear in the code length. Unsurprisingly, LDPC codes quickly attained their popularity in practical applications such as magnetic storage, wireless and optical communications. One, if not the most, important and challenging problem in LDPC code research is the study and analysis of the error floor phenomenon. This phenomenon is described as an abrupt degradation in the frame error rate performance of LDPC codes in the high signal-to-noise ratio region. Error floor is harmful because its presence prevents the LDPC decoder from reaching very low probability of decoding failure, an important requirement for many applications. Not long after the rediscovery of LDPC codes, scientists established that error floor is caused by certain harmful structures, most commonly known as trapping sets, in the Tanner representation of a code. Since then, the study of error floor mostly consists of three major problems: 1) estimating error floor; 2) constructing LDPC codes with low error floor and 3) designing decoders that are less susceptible to error floor. Although some parts of this dissertation can be used as important elements in error floor estimation, our main contributions are a novel method for constructing LDPC codes with low error floor and a novel class of low complexity decoding algorithms that can collectively alleviate error floor. These contributions are summarized as follows. A method to construct LDPC codes with low error floors on the binary symmetric channel is presented. Codes are constructed so that their Tanner graphs are free of certain small trapping sets. These trapping sets are selected from the Trapping Set Ontology for the Gallager A/B decoder. They are selected based on their relative harmfulness for a given decoding algorithm. We evaluate the relative harmfulness of different trapping sets for the sum-product algorithm by using the topological relations among them and by analyzing the decoding failures on one trapping set in the presence or absence of other trapping sets. We apply this method to construct structured LDPC codes. To facilitate the discussion, we give a new description of structured LDPC codes whose parity-check matrices are arrays of permutation matrices. This description uses Latin squares to define a set of permutation matrices that have disjoint support and to derive a simple necessary and sufficient condition for the Tanner graph of a code to be free of four-cycles. A new class of bit flipping algorithms for LDPC codes over the binary symmetric channel is proposed. Compared to the regular (parallel or serial) bit flipping algorithms, the proposed algorithms employ one additional bit at a variable node to represent its "strength." The introduction of this additional bit allows an increase in the guaranteed error correction capability. An additional bit is also employed at a check node to capture information which is beneficial to decoding. A framework for failure analysis and selection of two-bit bit flipping algorithms is provided. The main component of this framework is the (re)definition of trapping sets, which are the most "compact" Tanner graphs that cause decoding failures of an algorithm. A recursive procedure to enumerate trapping sets is described. This procedure is the basis for selecting a collection of algorithms that work well together. It is demonstrated that decoders which employ a properly selected group of the proposed algorithms operating in parallel can offer high speed and low error floor decoding.
Non-binary LDPC codes are flourishing in many areas for their excellent error correction performance in last decade. However, the bottleneck for NB-LDPC codes' implementation is the high decoding computational complexity. To seek for a low-complexity decoding algorithm, iterative double-reliability-based majority-logic decoding (IDRB-MLGD) algorithm has been proposed, which still suffers from relatively high error floor at BER level of 10-6. In this work, we propose a low-complexity coding scheme for non-binary LDPC code that bases on iterative IDRB-MLGD algorithm. The proposed work concatenates a Reed Solomon code with non-binary LDPC code which is decoded by IDRB-MLGD algorithm. By such concatenation, errors left by IDRB-MLGD algorithm are set into RS code blocks, which can be further reduced by these RS code blocks. Moreover, a low-complexity decoding algorithm is used to decode the RS code. The comparison results on decoding computational complexity indicate that concatenation only brings about trivial complexity increase. Simulation results show that this proposed concatenated coding scheme can trade off the performance and decoding computational complexity efficiently.
Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for optimization and performance evaluation of LDPC codes. The proposed FPGA framework includes several features such as the capability of changing the internal resolution of the decoder algorithm or capturing error patterns for error-floor analysis. Experimental results derived from the FPGA platform show that the designed QC-LDPC code is able to achieve an NCG of 11.6 dB at a bit-error-rate (BER) of 10-15with an overhead of 25% and a codeword length of only 16K bits.