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International Conference on Information, Communications & Signal Processing (ICICS)

A low-complexity coding scheme for non-binary LDPC code based on IDRB-MLGD algorithm

Xin Wei Xiao, Yichao Lu, Satoshi Goto

Published Dec 1, 2013• 3 citations
Publisher

Abstract

Non-binary LDPC codes are flourishing in many areas for their excellent error correction performance in last decade. However, the bottleneck for NB-LDPC codes' implementation is the high decoding computational complexity. To seek for a low-complexity decoding algorithm, iterative double-reliability-based majority-logic decoding (IDRB-MLGD) algorithm has been proposed, which still suffers from relatively high error floor at BER level of 10-6. In this work, we propose a low-complexity coding scheme for non-binary LDPC code that bases on iterative IDRB-MLGD algorithm. The proposed work concatenates a Reed Solomon code with non-binary LDPC code which is decoded by IDRB-MLGD algorithm. By such concatenation, errors left by IDRB-MLGD algorithm are set into RS code blocks, which can be further reduced by these RS code blocks. Moreover, a low-complexity decoding algorithm is used to decode the RS code. The comparison results on decoding computational complexity indicate that concatenation only brings about trivial complexity increase. Simulation results show that this proposed concatenated coding scheme can trade off the performance and decoding computational complexity efficiently.

DOI
10.1109/icics.2013.6782971

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Non-binary LDPC codes are flourishing in many areas for their excellent error correction performance in last decade. However, the bottleneck for NB-LDPC codes' implementation is the high decoding computational complexity. To seek for a low-complexity decoding algorithm, iterative double-reliability-based majority-logic decoding (IDRB-MLGD) algorithm has been proposed, which still suffers from relatively high error floor at BER level of 10-6. In this work, we propose a low-complexity coding scheme for non-binary LDPC code that bases on iterative IDRB-MLGD algorithm. The proposed work concatenates a Reed Solomon code with non-binary LDPC code which is decoded by IDRB-MLGD algorithm. By such concatenation, errors left by IDRB-MLGD algorithm are set into RS code blocks, which can be further reduced by these RS code blocks. Moreover, a low-complexity decoding algorithm is used to decode the RS code. The comparison results on decoding computational complexity indicate that concatenation only brings about trivial complexity increase. Simulation results show that this proposed concatenated coding scheme can trade off the performance and decoding computational complexity efficiently.
This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability-based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB- and ISRB-MLGD with limited complexity increase.
When the code is not long, non-binary low-density parity- check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes at the cost of higher decoding complexity. The recently developed iterative reliability-based majority-logic NB- LDPC decoding can achieve better performance-complexity tradeoffs than previous algorithms. Many existing NB-LDPC code construction schemes lead to quasi-cyclic or cyclic codes. In this paper, efficient low- complexity NB-LDPC decoder architectures are developed for these two types of codes based on the newly proposed iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Particularly, novel schemes are designed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. Moreover, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous decoders based on the Min-max algorithm, the proposed IHRB-MLGD decoder architectures can achieve tens of times higher efficiency for codes with similar length and rate with moderate coding gain loss.
Non-binary low-density parity-check (NB-LDPC) codes tend to exhibit much better performance than their binary counterparts while suffering from very high computational complexity. As a type of hard-decision NB-LDPC decoding algorithm, the iterative reliability-based majority-logic decoding (IRB-MLGD) algorithms are attractive for their low computation complexity, coming with obvious performance degradation. Aiming at improving the error-correction performance, in this paper, we introduce few redundant bits to the original NB-LDPC encoding and the corresponding checksum operations to the improved iterative soft reliability-based (IISRB)-MLGD. Based on the joint coding and decoding method, the obtained redundancy-aided (RA)-IISRB decoding algorithm shows significant performance improvement while maintaining the low-complexity property. Simulation results demonstrate that the proposed algorithm can achieve a more than 1.0dB extra coding gain over the original IISRB with a slight decrease of code rate.
Despite the performance of 5th Generation Low Density Parity Check (5G-LDPC) codes close to the capacity limit, the near-optimal floating-point BP decoding will lead to excessive use of hardware and high complexity of calculation. Thus, the quantized min-sum decoder with limited-precision is usually used in practical implementations. No matter using high or low precision quantization, some 5G-LDPC codes always suffer from the problem of high error floor, which affects their applications in future ultra-reliable scenarios. Using Reed-Solomon (RS) codes as the outer codes can significantly lower the error floor of 5G-LDPC codes due to their Hamming distance properties and excellent error-correction capability. In order to further improve the overall performance, an efficient iterative decoding algorithm of RS-LDPC concatenated codes is proposed in this paper. The proposed iterative algorithm of RS-LDPC codes can achieve noticeable gains over the 5G-LDPC codes at lower FER.
In the information theory , the non- binary low density parity check  (NB-LDPC) code is a  linear error correcting code , a method of transmitting message over a  noisy transmission channel. LDPCcodes are  capacity-approaching codes , which  means  that  practical constructions exist  that allow the noise threshold to be set very close to the theoretical maximum for a symmetric memory less channel.Using iterative  belief propagation techniques, NB-LDPC codes can be decoded in time linear to their block length. Non-binary low-density parity-check codes can achieve higher performance than their binary counterparts. Recently, two algorithms were developed for decoding NB-LDPC codes: iterative hard reliability-based majority-logic decoding (IHRB-MLGD) and iterative soft reliability-based majority-logic decoding (ISRB-MLGD has better performance-complexity tradeoffs than previous algorithms. This paper first proposes message-passing in such a way that we can reduce the memory consumption to a greater extent at the same time there should not be performance loss. By using enhanced iterative reliability-based majority-logic decoding algorithms we can achieve effective complexity-performance and noise free design. Compared to previous designs, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. This paper first proposes enhancement schemes to the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E-)IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Many existing NB-LDPC code construction methods lead to quasi-cyclic or cyclic codes. Both types of codes are considered in our design. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous designs based on the Min-max decoding algorithm, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.