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IEEE Transactions on Applied Superconductivity

Small-Area Sorting Network Based on Unary Coding Using Single Flux Quantum Circuits

Zeyu Han, Nobuyuki Yoshikawa, Yuki Yamanashi

Published Nov 7, 2024• 2 citations
Publisher

Abstract

The sorting network is crucial in fields like communication switching, data mining, image processing, neural networks, and others, where the bitonic sorting network (BSN) is an efficient comparison sorting method. It uses the compare-and-swap (CAS) units to compare two input data and decide whether to swap them. The single flux quantum (SFQ) circuits are well known for their high-speed operation and low power consumption, but they are less effective at performing numerical comparisons in CAS units. To address this issue, the unary coding (UC) method, an entropy encoding method that represents the natural number n with n ones followed by zeros, is introduced to implement a smaller SFQ-based BSN. The UC requires only AND and OR gates for CAS unit implementation. Consequently, the 8-input 32-bit UC BSN is two orders of magnitude smaller than the conventional SFQ binary coding BSN with the same precision and achieves approximately 3.3 times better energy efficiency. Additionally, compared to the CMOS-based UC BSN circuit, the energy efficiency improves by 5.8 times, even considering the cooling cost (×400). We also implemented a 4-input BSN circuit, using the 1.0 μm 10-layer Nb SFQ circuit fabrication process, and verified its operation at low speed.

DOI
10.1109/tasc.2024.3493881

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The sorting network is crucial in fields like communication switching, data mining, image processing, neural networks, and others, where the bitonic sorting network (BSN) is an efficient comparison sorting method. It uses the compare-and-swap (CAS) units to compare two input data and decide whether to swap them. The single flux quantum (SFQ) circuits are well known for their high-speed operation and low power consumption, but they are less effective at performing numerical comparisons in CAS units. To address this issue, the unary coding (UC) method, an entropy encoding method that represents the natural number n with n ones followed by zeros, is introduced to implement a smaller SFQ-based BSN. The UC requires only AND and OR gates for CAS unit implementation. Consequently, the 8-input 32-bit UC BSN is two orders of magnitude smaller than the conventional SFQ binary coding BSN with the same precision and achieves approximately 3.3 times better energy efficiency. Additionally, compared to the CMOS-based UC BSN circuit, the energy efficiency improves by 5.8 times, even considering the cooling cost (×400). We also implemented a 4-input BSN circuit, using the 1.0 μm 10-layer Nb SFQ circuit fabrication process, and verified its operation at low speed.
Due to their high-speed operation and low power consumption, single flux quantum (SFQ) circuits are promising technologies for integrated circuits. However, current superconducting fabrication limitations impose strict area constraints, challenging the construction of large-scale systems. Unary computing (UC) encodes numerical values by concentrating all “1”s at the beginning of a bit sequence. This approach enables arithmetic operations with fewer logic gates, thereby improving the area efficiency. In this study, we propose a novel high-capacity D flip-flop (HC-DFF) cell for UC-based SFQ circuits that achieves high-density data registration while preserving UC encoding. The HC-DFF employs a cascaded storage loop structure in which each loop sequentially stores one flux quantum, avoiding the margin deterioration associated with storing multiple flux quanta in a single loop. Simulation shows that the proposed HC-DFF achieves a bias margin of –20.8% to +32.7% and supports read/write operations above 100 GHz. We fabricated the HC-DFF using a 10 kA/cm² Nb four-layer superconducting process and verified its operation through low-speed measurements. The HC-DFF offers enhanced scalability and stability while reducing the number of required Josephson junctions by 83.3% per bit compared to conventional DFF-based shift registers for saving UC signals. For short unary sequences of less than 31 bits, it retains an advantage over storing binary data with equivalent precision using conventional DFF-based shift registers.
In superconducting circuits, information is carried by ps-wide, µV-tall, Single Flux Quanta (SFQ) pulses. These circuits can operate at frequencies of hundreds of GHz with orders of magnitude lower switching energy than complementary-metal-oxide-semiconductors (CMOS). However, under the stringent area constraints of modern superconductor technologies, fully-fledged, CMOS-inspired superconducting architectures cannot be fabricated at large scales. Unary SFQ (U-SFQ) is an alternative computing paradigm that addresses these area constraints. In U-SFQ, information is mapped to a combination of streams of SFQ pulses and in the temporal domain. In this work, we propose a U-SFQ Convolutional Neural Network (CNN) hardware accelerator capable of comparable peak performance with state-of-the-art superconducting binary (B-SFQ) approaches in 32× less area. CNNs can operate with 5 to 8 bits of resolution with no significant degradation in classification accuracy. The proposed CNN accelerator effortlessly supports this variable resolution and, for less than 7 bits, yields 5×-63× better performance than CMOS and 15×-173× better area efficiency than B-SFQ.
Most popular superconducting circuits operate on information carried by ps-wide, μV-tall, single flux quantum (SFQ) pulses. These circuits can operate at frequencies of hundreds of GHz with orders of magnitude lower switching energy than complementary-metal-oxide-semiconductors (CMOS). However, under the stringent area constraints of modern superconductor technologies, fully-fledged, CMOS-inspired superconducting architectures cannot be fabricated at large scales. Unary SFQ (U-SFQ) is an alternative computing paradigm that can address these area constraints. In U-SFQ, information is mapped to a combination of streams of SFQ pulses and in the temporal domain. In this work, we extend U-SFQ to introduce novel building blocks such as a multiplier and an accumulator. These blocks reduce area and power consumption by 2 ×\times× and 4 ×\times× compared with previously proposed U-SFQ building blocks and yield at least 97% area savings compared with binary approaches. Using these multiplier and adder, we propose a U-SFQ Convolutional Neural Network (CNN) hardware accelerator capable of comparable peak performance with state-of-the-art superconducting binary approach (B-SFQ) in 32 ×\times× less area. CNNs can operate with 5–8 bits of resolution with no significant degradation in classification accuracy. For 5 bits of resolution, our proposed accelerator yields 5 ×\times× to 63 ×\times× better performance than CMOS and 15 ×\times× to 173 ×\times× better area efficiency than B-SFQ.
Abstract Reversible logic synthesis is becoming a significant research component for post-CMOS computing devices, particularly quantum computing. In this work we connect the reversible logic synthesis problem to sorting algorithms. Reversible logic has emerged as a promising technology in recent years, with applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical gates AND, OR, and XOR are not reversible. This paper employs the control swap gate to implement a 2x2 switch. In multiprocessor system different computing operations are performed concurrently to get higher throughput. Sorting network can be used to tie up different parts of a large complex system efficiently with least amount of hardware to perform concurrent operations. A sorting network can be built using a multiple input and multiple output switching network. Following the implementation of the 2x2 switch, a bitonic sorting circuit is designed. The goal of developing a reversible sorting circuit is to reduce power consumption while maintaining reliable communication. The bitonic sorting circuit was successfully implemented, and the output was simulated in IBM qiskit. This presents efficient sorting circuit that can sort binary numbers in ascending/descending order.
Abstract Single-flux-quantum (SFQ) circuits are promising candidates for post-Moore integrated circuits owing to their ultra-high-speed operation and low power consumption. However, limitations in current superconducting fabrication processes pose significant challenges to achieving area-efficient SFQ-based microprocessors, particularly in the design of compact arithmetic logic units (ALUs). Unary computing enables arithmetic operations using extremely simple logic, but typically suffers from long computation latency. This paper focuses on unary computing for superconducting circuits that exploits the complementary characteristics of SFQ logic and unary computing. The ultra-high-speed nature of SFQ circuits compensates for the inherent latency of unary computation, while unary computing enables an ultra-low hardware cost by substantially reducing circuit complexity. Based on this concept, we introduce a unary computing methodology tailored for SFQ circuits and design a superconducting unary ALU with ultra-low hardware cost. The proposed ALU requires only 183 Josephson junctions (JJs), achieving approximately 88.2% reduction in JJ count and 80.4% reduction in area compared with a conventional bit-serial SFQ ALU. The proposed design, including binary-to-unary and unary-to-binary converters, was fabricated using a 10 kA cm −2 Nb four-layer superconducting circuit fabrication process and experimentally verified to operate correctly at approximately 72 GHz. The total power consumption at this frequency is approximately 58.9 µ W. This work quantitatively demonstrates the effectiveness of combining unary computing with SFQ circuits for ultra-low-cost processing systems and provides superconducting circuits as a new design option for alternative computation paradigms, such as unary computing.
Background: The synthesis of reversible logic has gained prominence as a crucial research area, particularly in the context of post-CMOS computing devices, notably quantum computing. Objective: To implement the bitonic sorting circuit, 2x2 switch, is used. The overarching objective of implementing a reversible sorting circuit is to mitigate power consumption while promising secure communication. The successful implementation of the bitonic sorting circuit utilizing the proposed 2x2 switch is validated through simulations conducted in IBM Qiskit. Methods: This study begins by employing the control swap gate to implement a 2x2 switch, aimed at enabling concurrent computing operations within multiprocessor systems to enhance throughput. Subsequently, following the successful implementation of the 2x2 switch, the study proceeds to design a bitonic sorting circuit. Results: Bitonic sort using a 2x2 switch on the IBM Quantum Experience (IBMQ) platform via the QISKit SDK in Python 3.6. Specifically, Qiskit v0.29.0 is utilized, with OpenQASM. OpenQASM serves as the quantum assembly and instruction language. Conclusion: This work presents a methodology for constructing a 2x2 switch, utilizing a reversible control swap gate as its core component. Additionally, it demonstrates the intricate development and implementation of a bitonic sorting circuit, capitalizing on this innovative switch architecture.