The quantum computing (QC) is emerging as one of the possibilities to replace the conventional computing to meet the complex computing challenges. Quantum gates are based on the quantum mechanical phenomena such as superposition and entanglement. Moreover, there are several ways to realize the reversible full adder representing one of the building blocks of the reversible computing. One of the ways to realize the reversible full adder is by using the controlled V and V+ gates. Spintronics is one of the quantum technologies to realize the reversible computing physically. Therefore, there is need of spin-torque based modelling of controlled V and V+ gates for the quantum computing applications in the reversible computing domain. In this paper, the controlled V and V+ gates are modelled for the spin-torque based qubit architecture through the optimization at elementary single-qubit rotation and two-qubit entanglement level. Therefore, the key innovation or unique contribution is to realize the controlled V and V+ gates by using the minimum number of the elementary operations (single- and two-qubits). Moreover, a quantum full adder (QFA) composed of controlled V and V+ gates, is optimized and realized with the spin-torque models of the controlled V and V+ gates to achieve fault tolerant fidelity. Therefore, the novelty is that the optimization of the controlled V and V+ gates for the reversible full adders is carried out by using the identity rules.
The quantum computing (QC) is emerging as one of the possibilities to replace the conventional computing to meet the complex computing challenges. Quantum gates are based on the quantum mechanical phenomena such as superposition and entanglement. Moreover, there are several ways to realize the reversible full adder representing one of the building blocks of the reversible computing. One of the ways to realize the reversible full adder is by using the controlled V and V+ gates. Spintronics is one of the quantum technologies to realize the reversible computing physically. Therefore, there is need of spin-torque based modelling of controlled V and V+ gates for the quantum computing applications in the reversible computing domain. In this paper, the controlled V and V+ gates are modelled for the spin-torque based qubit architecture through the optimization at elementary single-qubit rotation and two-qubit entanglement level. Therefore, the key innovation or unique contribution is to realize the controlled V and V+ gates by using the minimum number of the elementary operations (single- and two-qubits). Moreover, a quantum full adder (QFA) composed of controlled V and V+ gates, is optimized and realized with the spin-torque models of the controlled V and V+ gates to achieve fault tolerant fidelity. Therefore, the novelty is that the optimization of the controlled V and V+ gates for the reversible full adders is carried out by using the identity rules.
Quantum computing (QC) imitates particle behavior at the sub-atomic level. Quantum gates are based on quantum mechanical phenomena such as superposition and entanglement. The obstacle to the realization of reversible computing is the huge number of operations in terms of quantum gates. Therefore, novel designs of reversible computing blocks with a minimum number of elementary operations with high fidelity are necessary. Therefore, a novel design of multiplexer is proposed in this article, which is composed of only 1-CNOT and 1-Toffoli gates. Moreover, the reduced decomposition of the multiplexer and its identity rule-based optimization for the spin-torque-based n-qubit architecture is discussed. To validate the design, the QISKIT implementation of the novel design in terms of amplitude, probability, and Q-sphere representation is carried out. The results are encouraging to realize the reversible computing involving quantum multiplexer as one of the building blocks.
Abstract Quantum computing (QC) is suitable for reversible computing due to its inherent parallel processing ability and fast speed. It also helps to address the issue of high-power dissipation in classical computing. Moreover, QC gates are the sequence of elementary operations such as single-qubit rotation and two-qubit entanglement. Elementary quantum operations are required to be reduced for the realization of complex computing. In this paper, optimization of 1-Toffoli gate-based quantum full adders (QFAs) in terms of the number of elementary operations with the help of quantum library {Ry, Rz, SWAP SWAP } is carried out. Moreover, the performance of two different 1-Toffoli QFAs is investigated in terms of execution time, fidelity, and number of electrons required to realize the QFAs. Improvement in fidelity is 0.7% and 0.57% for QFA1 and QFA2, respectively, compared to the fidelity of 2-Toffoli QFA. A 9.97% increase in execution time is mandatory for the QFA2 compared to QFA1. The QFA2 takes 5% more number of electrons in comparison to QFA1.
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.
Currently, computing paradigm is ruled by the laws of classical physics and will continue till the dimensions of transistors reaches the size of atomic particles. Quantum computing (QC) is a new technology that employs laws of quantum mechanics to address issues such as irreversibility and power dissipation that are outside the scope of conventional computing models. QC offers a powerful stage for solving complex and compound problems like searching and number factoring. A critical task in utilizing quantum physics in many application fields is circuit design using reversible quantum gates. Unitary decomposition is a popular scheme for mapping quantum algorithms to any set of elementary quantum operations. Using decomposition techniques enables transformation of unitary matrices into fundamental quantum gates, which is critical for running algorithms on prevailing quantum computers. Any 3x3 reversible quantum gate can be decomposed into single-qubit rotation gates and two qubit CNOT gates. This paper is the first to present quantum implementations of FRSG1 and JTF1 gates into CNOT gates and single qubit U3 gates with different optimization levels on a platform provided by IBM. These gates are important in a variety of practical applications like Stochastic computing and parity generation circuits. In FRSG1 the implementation count of single qubit gates decreases by 56% and the count of two qubit gates by 15% after optimization, whereas in JTF1 gate the single qubit gate count reduces by 71% and the number of two qubit gates reduces by 41%.
Quantum computing is gaining importance as a promising approach for achieving energy-efficient and reliable computation, where reversible logic circuits play a key role. Full adders are fundamental components of arithmetic and logic units, and their correct operation is essential for overall system performance. With continued technology scaling, digital circuits are increasingly affected by manufacturing defects and permanent faults, making fault modeling and testability analysis critically important. Among various fault models, the stuck-at fault model is widely used due to its simplicity and its ability to represent common physical defects. This paper presents a detailed stuck-at fault analysis of a reversible full adder designed using Peres gates. The proposed architecture efficiently generates Sum and Carry outputs while reducing gate count and information loss. To evaluate practical feasibility, the full adder is implemented on the IBM quantum computing platform using IBM Composer and simulated through the Qiskit framework. Both fault-free and faulty conditions are examined by introducing stuck- at-0 and stuck-at-1 faults at key nodes affecting the Sum and Carry outputs. State-vector analysis, probability distributions, and measurement results are obtained for all possible input combinations. The exhaustive fault analysis achieves a fault coverage of 87.5% for both SA-0 and SA-1 conditions, indicating high fault observability. The results confirm that the proposed Peres gate–based reversible full adder is well suited for fault-tolerant arithmetic applications in reversible and quantum computing environments.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.