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IEEE Journal of Solid-State Circuits

A Cryo-CMOS Controller With Class-DE Driver and DC Magnetic-Field Tuning for Quantum Computers Based on Color Centers in Diamond

Niels Fakkel, Luc Enthoven, Jiwon Yun, Margriet van Riggelen, Hendrik Benjamin van Ommen, Kai-Niklas Schymik, Hans P. Bartling, Eftychia Tsapanou Katranara, René Vollmer, T. H. Taminiau, Masoud Babaie, Fabio Sebastiano

Published Sep 26, 2024• 11 citations
Publisher

Abstract

Striving toward a scalable quantum processor, this article presents the first cryo-CMOS quantum bit (qubit) controller targeting color centers in diamond. Color-center qubits enable a modular architecture that allows for the 3-D integration of photonics, cryo-CMOS control electronics, and qubits in the same package. However, performing quantum operations in a scalable manner requires large currents in the driving coils due to low coil-to-qubit coupling. Moreover, active calibration of the qubit Larmor frequency is required to compensate inhomogeneities of the bias magnetic field. To overcome these challenges, this work proposes both a cryo-CMOS alternating current (AC) controller consisting of a class-DE series-resonant driver and a DC current regulator (DC CR) that uses a triode-biased H-bridge for scalable low-power qubit operations. By experimentally validating the cryo-CMOS performance with a nitrogen-vacancy (NV) color-center qubit, the AC controller can drive a Rabi oscillation up to 2.5 MHz with a supply draw of 6.5 mA, and the DC CR can tune the Larmor frequency by ±9 MHz while driving up to ±20 mA in the bias coil.$T_{2}^{*}$coherence times up to$5.3~\mu $s and single-qubit gate fidelities above 98% are demonstrated with the cryo-CMOS control using Ramsey experiments and gate set tomography (GST), respectively. The results demonstrate the efficacy of the proposed cryo-CMOS chips and enable the development of a modular quantum processor based on color centers.

DOI
10.1109/jssc.2024.3459392

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Striving toward a scalable quantum processor, this article presents the first cryo-CMOS quantum bit (qubit) controller targeting color centers in diamond. Color-center qubits enable a modular architecture that allows for the 3-D integration of photonics, cryo-CMOS control electronics, and qubits in the same package. However, performing quantum operations in a scalable manner requires large currents in the driving coils due to low coil-to-qubit coupling. Moreover, active calibration of the qubit Larmor frequency is required to compensate inhomogeneities of the bias magnetic field. To overcome these challenges, this work proposes both a cryo-CMOS alternating current (AC) controller consisting of a class-DE series-resonant driver and a DC current regulator (DC CR) that uses a triode-biased H-bridge for scalable low-power qubit operations. By experimentally validating the cryo-CMOS performance with a nitrogen-vacancy (NV) color-center qubit, the AC controller can drive a Rabi oscillation up to 2.5 MHz with a supply draw of 6.5 mA, and the DC CR can tune the Larmor frequency by ±9 MHz while driving up to ±20 mA in the bias coil.T2∗T_{2}^{*}T2∗​coherence times up to5.3 μ5.3~\mu 5.3 μs and single-qubit gate fidelities above 98% are demonstrated with the cryo-CMOS control using Ramsey experiments and gate set tomography (GST), respectively. The results demonstrate the efficacy of the proposed cryo-CMOS chips and enable the development of a modular quantum processor based on color centers.
Color-center quantum bits (qubits), such as the Nitrogen-Vacancy center (NV) in diamond, have demonstrated entanglement between remote (>1.3km) qubits and excellent coherence times [1], all while operating at a few Kelvins. Compared to other qubit technologies typically operating at mK temperatures, the higher operating temperature of NVs enables scalable 3D integration with cryo-CMOS control electronics [2], provides significantly more cooling power, and removes the interconnect bottleneck between the qubits and the electronics in prior art [3–5]. Yet, no cryo-CMOS controller for NV-based quantum computers (QC) has been demonstrated.
Utility-scale quantum technologies will not only require a well-performing quantum platform, but also classical control hardware that is scalable, efficient, and meets the design requirements set by the quantum system of interest. One approach is the application of silicon CMOS technology, a highly scalable and mature technology, to design application-specific integrated circuits (ASIC) that are optimized for the quantum system. In this work, we present two-qubit control of electron and nuclear spins in NV centres in diamond, using a cryogenic CMOS qubit controller integrated with a diamond quantum device in a cryostat. Using Gate Set Tomography (GST) we characterize the performance of the single-qubit gates on both electron- and carbon nuclear spins, and analyze the limiting noise processes. We use dynamical decoupling to engineer a two-qubit gate, and estimate F2q,avg=95(2)%F_\text{2q,avg} = 95(2)\%F2q,avg​=95(2)% for the electron-nuclear two-qubit gate fidelity. Our demonstration of cryo-CMOS-driven two-qubit gates is a key step towards highly-integrated quantum devices based on colour centres.
We present a scalable cryo-CMOS controller for color-center-based quantum processors. A diamond waveguide micro-chiplet with NVs is pick-and-placed on CMOS with a 3D-printed prism for scalable photonic readout. A serial qubit driver array using grid inductors and pulse-width modulators generates a programmable 2.87GHz magnetic field for each qubit with low power and strong confinement. Up to 144 qubits can be operated on a single chip, with204μW204\mu\mathrm{W}204μWpower consumption per qubit under active control.
Quantum processors based on color centers in diamond are promising candidates for future large-scale quantum computers thanks to their flexible optical interface, (relatively) high operating temperature, and high-fidelity operation. Similar to other quantum computing platforms, the electrical interface required to control and read out such qubits may limit both the performance of the whole system and its scalability. To address this challenge, this work analyzes the requirements of the electrical interface and investigates how to efficiently implement the electronic controller in a scalable architecture comprising a large number of identical unit cells. Among the different discussed functionalities, a specific focus is devoted to the generation of the static and dynamic magnetic fields driving the electron and nuclear spins, because of their major impact on fidelity and scalability. Following the derived requirements, different system architectures, such as a qubit frequency-multiplexing scheme, are considered to identify the most power efficient approach, especially in the presence of inhomogeneity of the qubit Larmor frequency across the processor. As a result, a non-frequency-multiplexed 1- mm2\,\mathrm{m}\mathrm{m}^{2}mm2unit-cell architecture is proposed as the optimal solution, able to address up to one electron-spin qubit and nine nuclear-spin qubits within a 3-mW average power consumption, thus establishing the baseline for the scalable electrical interface for future large-scale color-center quantum computers.
Abstract Realizing a practically useful superconducting quantum computer will require a dramatic scale-up of quantum control electronics to meet the growth in required qubit counts. Conventional rack-based room-temperature control electronics impose severe constraints on wiring density, cost, and system footprint, creating a barrier to large-scale and fault-tolerant quantum computing. Here we demonstrate a hybrid quantum control architecture that combines cryogenic complementary metal-oxide semiconductor (cryo‑CMOS) application-specific integrated circuits (ASICs) for two‑qubit flux control with room‑temperature radio‑frequency electronics for single‑qubit control and readout. The resulting system achieves high density and scalable quantum control without compromising two‑qubit gate fidelity. Deployed on a 156‑qubit quantum processor, the cryo-CMOS subsystem achieves two‑qubit gate errors at the {10}^{-3} level, with a best randomized benchmarking error per gate of 8.4\times{10}^{-4}, stable operation over multi‑day timescales, and no measurable performance degradation as we increase the temperature of the cryo-CMOS ASICs from 7 to 20 K. Thermal analysis identifies cryo-CMOS chip operation near 20 K as a favorable regime, enabling efficient cooling of a large number of channels per cryostat. Compared against rack‑based flux-control, the cryo-CMOS subsystem achieves statistically indistinguishable two-qubit gate fidelities under matched gate settings and enables a tenfold improvement in system spatial footprint. These results establish cryo‑CMOS flux control as a practical and scalable foundation for large‑scale and fault-tolerant superconducting quantum systems.