Quantum computing is currently in the era of Noisy-Intermediate-Scale Quantum (NISQ), where superconducting quantum chips can only support two-qubit gates between adjacent physical qubits. This constraint necessitates the insertion of SWAP gates during circuit mapping to ensure that the nearest neighbor requirements are met on actual quantum computing devices. In this work, based on the circuit partitioning and unitary matrix decomposition mechanism, an equivalent transformation form of quantum circuit is given to reduce the number of two-qubit gates in the target quantum circuit. Experimental results demonstrate that the decomposed equivalent circuits have a shorter depth, with an average optimization rate of 18.41%. Our proposed optimization method effectively reduces the number of two-qubit gates in quantum circuits, enhancing the efficiency of mapping on NISQ devices.
Quantum computing is currently in the era of Noisy-Intermediate-Scale Quantum (NISQ), where superconducting quantum chips can only support two-qubit gates between adjacent physical qubits. This constraint necessitates the insertion of SWAP gates during circuit mapping to ensure that the nearest neighbor requirements are met on actual quantum computing devices. In this work, based on the circuit partitioning and unitary matrix decomposition mechanism, an equivalent transformation form of quantum circuit is given to reduce the number of two-qubit gates in the target quantum circuit. Experimental results demonstrate that the decomposed equivalent circuits have a shorter depth, with an average optimization rate of 18.41%. Our proposed optimization method effectively reduces the number of two-qubit gates in quantum circuits, enhancing the efficiency of mapping on NISQ devices.
Abstract With the rapid development of quantum computing, quantum computing devices have entered the Noisy Intermediate-Scale Quantum(NISQ)era. However, current NISQ quantum computing devices still face the challenge of physical limitations. To enable quantum algorithms to be directly executed on quantum computing devices, high-level quantum gates (such as MCT gates) in quantum circuits need to be decomposed and mapped onto quantum computing devices. This paper proposes a quantum device-aware method for decomposing high-level quantum gates. This method selects an optimal sub-topology of the quantum device as the target based on the circuit scale and the goal of reducing error rates. According to the proposed MCT gate decomposition rules, an associated gate-pairs generation algorithm is designed to facilitate subsequent decomposition. The control bits of the MCT gates are partitioned based on the associated gate-pair to better match the selected sub-topology. After eliminating redundant gates through the inverse decomposition of associated gate-pairs, the mapping is performed. Experimental results show that the proposed decomposition method reduces the number of basic quantum gates in quantum circuits, with an average optimization rate of 14.6%. For benchmark circuits decomposed using the method, applying the routing algorithm for mapping requires fewer additional gates, with an average optimization rate of 20.6%. The fidelity of the circuits improved by an average of 14.1% after mapping.
In recent years, the emergence of the Noisy Intermediate-Scale Quantum (NISQ) era has led to the development of a wide variety of quantum devices, marking a dynamic phase in the field of quantum computing. Despite these advancements, practical applications of quantum computers still face significant challenges, one of the most prominent being the limited connectivity between physical quantum bits (qubits). This limitation requires quantum circuits to be recompiled through layout synthesis before they can be executed on quantum devices. Layout synthesis determines the specific placement of quantum gates within the circuit on the physical hardware. When gates do not align with the connectivity constraints of the device, additional quantum gates must be inserted to remap the qubits, which can negatively affect the circuit’s efficiency and performance. To address this issue, the primary goal of this paper is to enhance the mapping process within layout synthesis, aiming to optimize both the layout and the circuit depth. Experimental results demonstrate that the proposed method effectively reduces the quantum circuit depth, outperforming other existing approaches in terms of efficiency.
In the era of noisy intermediate-scale quantum (NISQ) computing, the limited connectivity between qubits is one of the common physical limitations faced by current quantum computing devices. Quantum circuit mapping methods transform quantum circuits into equivalent circuits that satisfy physical connectivity constraints by remapping logical qubits, making them executable. The optimization problem of quantum circuit mapping has NP-hard computational complexity, and existing heuristic mapping algorithms still have significant potential for optimization in terms of the number of quantum gates generated. To reduce the number of SWAP gates inserted during mapping, the solution space of the mapping problem is represented as a tree structure, and the mapping process is equivalent to traversing this tree structure. To effectively and efficiently complete the search process, a beam search framework (BSF) is proposed for solving quantum circuit mapping. By iteratively selecting, expanding, and making decisions, high-quality target circuits are generated. Experimental results show that this method can significantly reduce the number of inserted SWAP gates on medium to large circuits, achieving an average reduction of 44% compared to baseline methods, and is applicable to circuits of various sizes and complexities.
With the rapid development of the field of quantum computing, quantum computing devices have entered the era of noisy intermediate-scale quantum (NISQ). However, current NISQ quantum computing devices still face the challenge of physical constraints. In order to enable quantum algorithms to be directly executed on quantum computing devices, it is necessary to decompose the advanced quantum gates (such as the MCT gate) in the quantum circuit and map them onto the quantum computing devices. This paper proposes a decomposition method for advanced quantum gates that is aware of the two-dimensional topological structure. Based on the proposed decomposition rules of the MCT gate, this method designs a search algorithm for associated gate pairs that is conducive to subsequent decomposition, and divides the control bits of the MCT gate based on the associated gate pairs, making the division method more adaptable to the topological structure. After the associated gate pairs are inversely decomposed to eliminate redundant gates, the circuit mapping is carried out. The experimental results show that the decomposition method proposed in this paper can reduce the number of basic quantum gates in the quantum circuit, with an average optimization rate of 14.6%; for the benchmark circuits using the decomposition method in this paper, when the routing algorithm is applied for mapping, the number of additional gates required is smaller, with an average optimization rate of 20.6%.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale.
In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
In order to implement a quantum circuit on an NISQ device, it must be transformed into a functionally equivalent circuit that satisfies the device's connectivity constraints. However, NISQ devices are inherently noisy, and minimizing the number of SWAP gates added to the circuit is crucial for reducing computation errors. To achieve this, we propose a subgraph isomorphism algorithm based on the timing weight priority of quantum gates, which provides a better initial mapping for a specific two-dimensional quantum architecture. Additionally, we introduce a heuristic swap sequence selection optimization algorithm that uses a distance optimization measurement function to select the ideal sequence and reduce the number of SWAP gates, thereby optimizing the circuit transformation. Our experiments demonstrate that our proposed algorithm is effective for most benchmark quantum circuits, with a maximum optimization rate of up to 43.51% and an average optimization rate of 13.51%, outperforming existing related methods.