The serial and/or parallel execution of Grover's algorithm

茂 山下

Radu-Iulian Gheorghica

The purpose of the research presented in this paper is finding the best execution times for searching subgraph isomorphisms. For this was created the GR3 Algorithm, its design consisting of a combination of Parallel Programming and Quantum Computing. The obtained execution times are significantly small. Thus can be deduced that an approach such as this is superior in obtaining the required results. The original contribution consists in studying a Parallel Programming approach combined with Quantum Computing Circuits and Grover’s Algorithm for searching subgraph isomorphisms using a laptop and real quantum computers [16].

Issac Diana Jeba Jingle, Sharlene Anna Pereira

Y. H. Lee, Mohamed Khalil-Hani, Muhammad Nadzir Marsono

Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

Mihai-Zicu Mina, Emil Simion

Folkert de Ronde, Alexander Knapen, Stephan Wong +1 more

As quantum computers continue to improve and support larger, more complex computations, smart control hardware and compilers are needed to efficiently leverage the capabilities of these systems. This paper introduces a novel approach to enhance the execution of quantum algorithms on distributed quantum systems. The proposed method involves the development of a hardware design that supports parallel instruction execution and a compiler that modifies the order of instructions to increase parallelism opportunities. The hardware design can be flexibly configured to facilitate parallel execution of instructions that have identical parameters. Furthermore, the compiler uses the underlying hardware constraints to intelligently reorder and decompose instructions to avoid dependencies. The compiler, hardware, and their combination are evaluated using a runtime calculator and a benchmark quantum algorithm set. The results demonstrate a significant speedup, achieving a maximum average speedup of 16.5x and a maximum single-benchmark speedup of 56.2x relative to a baseline, serial execution model. Furthermore, we show a speedup can be obtained across all benchmarks using any of the proposed hardware schemes, although the degree of speedup is largely dependent on the type of quantum algorithm. Taken together, the results of this paper represent a significant step towards realizing high-performance quantum computing systems.