Superconducting electronics have garnered significant attention recently due to their exceptional speed and energy efficiency. They play a vital role in scaling quantum computers to thousands of qubits and offer unique advantages for high-performance computing and aerospace exploration. However, conventional Josephson junction-based superconducting circuits face scalability challenges due to flux trapping and struggle in driving high load impedances. To address these issues, three-terminal cryotron devices have emerged as a promising alternative. Here, we present a novel approach utilizing two heater cryotron devices to construct an XNOR gate, significantly enhancing the area efficiency of existing superconducting XNOR gates. XNOR logic plays a pivotal role in various applications including adder design, data center operations like copy verification and data encryption/decryption. Our designed XNOR logic gate boasts a substantial improvement in area efficiency compared to existing designs, requiring only two heater cryotron devices instead of the previous requirement of ten cryotron devices, leading to an 80% improvement in device count. This advancement holds promise for further optimizing superconducting circuitry for various applications.
Superconducting electronics have garnered significant attention recently due to their exceptional speed and energy efficiency. They play a vital role in scaling quantum computers to thousands of qubits and offer unique advantages for high-performance computing and aerospace exploration. However, conventional Josephson junction-based superconducting circuits face scalability challenges due to flux trapping and struggle in driving high load impedances. To address these issues, three-terminal cryotron devices have emerged as a promising alternative. Here, we present a novel approach utilizing two heater cryotron devices to construct an XNOR gate, significantly enhancing the area efficiency of existing superconducting XNOR gates. XNOR logic plays a pivotal role in various applications including adder design, data center operations like copy verification and data encryption/decryption. Our designed XNOR logic gate boasts a substantial improvement in area efficiency compared to existing designs, requiring only two heater cryotron devices instead of the previous requirement of ten cryotron devices, leading to an 80% improvement in device count. This advancement holds promise for further optimizing superconducting circuitry for various applications.
Superconducting electronics are among the most promising alternatives to conventional CMOS technology, thanks to the ultra-fast speed and ultra-high energy efficiency of the superconducting devices. Having a cryogenic control processor is also a crucial requirement for scaling the existing quantum computers up to thousands of qubits. Despite showing outstanding speed and energy efficiency, Josephson junction-based circuits suffer from several challenges such as flux trapping leading to limited scalability, difficulty in driving high impedances, and so on. Three-terminal cryotron devices have been proposed to solve these issues, which can drive high impedances (>100 kΩ) and are free from any flux trapping issue. In this work, we develop a reconfigurable logic circuit using a heater cryotron (hTron). In conventional approaches, the number of devices to perform a logic operation typically increases with the number of inputs. However, here, we demonstrate a single hTron device-based logic circuit that can be reconfigured to perform 1-input copy and NOT, 2-input AND and OR, and 3-input majority logic operations by choosing suitable biasing conditions. Consequently, we can perform any processing task with a much smaller number of devices. Also, since we can perform different logic operations with the same circuit (same layout), we can develop a camouflaged system where all the logic gates will have the same layout. Therefore, this proposed circuit will ensure enhanced hardware security against reverse engineering attacks.
Superconducting (SC) electronics (SCE) is one of the major requirements to develop a large-scale practical quantum computing system. (Figs. 1(a)) [1]. Currently, a room temperature conventional computer is used as the control processor which requires a huge number of lossy interconnects to connect with the qubits placed at a few millikelvin temperatures. This, in turn, limits the scalability of the quantum computing system up to hundreds of qubits which is not enough to achieve the full potential [2]. Therefore, along with a suitable cryogenic memory, a cryogenic (preferably superconducting) control processor is required to develop a quantum computing system with thousands of qubits. Moreover, SCE offers ultra-fast (hundreds of gigahertz) and highly energy efficient (sub attojoule/bit) performance [3]. Therefore, SCE is projected to achieve the department of energy (DOE) exascale goal which the conventional supercomputers failed to achieve (Fig. 1(b)) [4]. However, Josephson junction-based SC circuits suffer from limited integration density due to flux trapping, difficulty in driving large impedances, fanning out digital signals, and operating in noisy environments [5]. To address these existing issues, here, we present a novel reconfigurable SC logic circuit using a nano-cryotron (nTron) that can perform 1-input copy, 2-input AND and OR, and 3-input majority logic functionalities. This work can enable the implementation of highly scalable and energy-efficient SC processor since the use of only one device. To achieve the reconfigurable nature of the logic circuit, we utilize the multi-gate switching of nTron.
The growing demand for ultra low power computing and the emergence of quantum technologies have intensified interest in cryogenic electronics, particularly superconducting devices. Despite their promise, current controlled superconducting components face fundamental challenges in cascadability, limiting their effectiveness in complex logic architectures. To overcome this, recent efforts have focused on developing gate tunable superconducting devices, such as Josephson junction field effect transistors (JJFETs). However, achieving robust control and sufficient supercurrent gain, both critical for transistor-like performance in logic circuits remains a key challenge. A recent advancement in JJFET design, based on InAs and GaSb heterostructures, demonstrates enhanced gain and favorable device characteristics suitable for circuit integration. Building on this innovation, we propose and analyze fundamental voltage controlled logic topologies using the quantum enhanced JJFET. We develop a Verilog A based circuit compatible compact model of the quantum enhanced JJFET which accurately captures the experimentally observed device characteristics. To ensure cascadability, our logic circuits incorporate the multilayered Heater Nanocryotron (nTron), a superconducting nanowire-based thermal switch. Through simulation based analysis, we demonstrate the successful implementation of fundamental logic gates, including NOT, NAND, and NOR. Furthermore, we design a 3 input majority gate, which plays a pivotal role in quantum and reversible computing due to its universality. Finally, to demonstrate the cascadability of our proposed logic topology, we demonstrate the operation of a 2 input XOR gate based on our designed JJFET based NOT, NAND, and NOR gate.
Superconducting electronics have emerged as a promising platform for advanced information processing, offering unique opportunities for on chip computation and signal manipulation at cryogenic temperatures. These devices hold particular potential in applications ranging from quantum computing to high sensitivity magnetic sensing, where integrated logic and scalable circuit architectures are essential for performing complex computational and signal-processing tasks. In this work, we present a dual-input multilayered heater nanocryotron (hTron) that introduces both multi input functionality and reconfigurable logic capability within a single device. This capability represents a step forward toward realizing more complex computational architectures. In addition, we demonstrate that these devices can, in principle, drive one another and potentially be integrated on a larger scale. Furthermore, the inherent reconfigurability of the demonstrated device allows for dynamic switching between logic operations without requiring additional components which reduces circuit area and simplifies cryogenic and biasing requirements, making the design highly suitable for scalable superconducting computing systems.
The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process.
Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.