Achieving fault tolerance in quantum computing demands sophisticated control systems, and their development is advancing rapidly. To keep pace with fast-moving qubit technology, these systems are typically prototyped on field-programmable gate arrays (FPGAs)-reconfigurable devices that can adapt to a wide range of qubit counts and connectivity patterns, as well as to various error-correction codes. Nevertheless, application-specific integrated circuits (ASICs)-despite being fixed after fabrication and incurring substantial non-recurring engineering costs-ultimately offer higher performance. This paper presents a case study of the error decoder, a core control system component, and quantitatively compares its FPGA and ASIC implementations. The results offer guidance for future control system design.
Quantum error correction (QEC) is essential for scalable quantum computing. However, it requires classical decoders that are fast and accurate enough to keep pace with quantum hardware. While quantum low-density parity-check codes have recently emerged as a promising route to efficient fault tolerance, current decoding algorithms do not allow one to realize the full potential of these codes in practical settings. Here, we introduce a convolutional neural network decoder that exploits the geometric structure of QEC codes, and use it to probe a novel "waterfall" regime of error suppression, demonstrating that the logical error rates required for large-scale fault-tolerant algorithms are attainable with modest code sizes at current physical error rates, and with latencies within the real-time budgets of several leading hardware platforms. For example, for the
[144,12,12] Gross code, the decoder achieves logical error rates up to
∼17x below existing decoders - reaching logical error rates
∼10−10 at physical error
p=0.1% - with 3-5 orders of magnitude higher throughput. This decoder also produces well-calibrated confidence estimates that can significantly reduce the time overhead of repeat-until-success protocols. Taken together, these results suggest that the space-time costs associated with fault-tolerant quantum computation may be significantly lower than previously anticipated.
In this thesis, we explore practical areas in the theory of quantum error correction that have become especially relevant in light of recent experimental advances. We address the question of whether classical decoding calculations, which are required in order to detect, track and correct errors, can be performed in real-time at a sufficient pace to keep up with the quantum clock speed. Our investigation includes consideration of practical details, such as the communication bandwidth that is required for the classical decoder to interact with the quantum control hardware. We consider the technique of post-selection, which is often used to boost logical performance in small-scale experimental demonstrations of quantum error correction. In particular, we address the common criticism that post-selection is not scalable, and investigate applications of post-selection for medium-scale state preparation circuits, which will continue to be relevant in large-scale quantum computers. Finally, we address the problem of circuit design, whereby theoretical constructs from quantum error correction are translated into a gate-level set of instructions that can be executed on hardware, and in particular we search for time-optimal circuits for detecting errors in topological codes.