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IEEE Signal Processing Letters

High-Performance QC-LDPC Layered Decoder Based on Shortcut Updating

Zhongyong Wang, Zhaoyan Xie, Kexian Gong, Jin Yan, Lianghui Chen

Published Jan 1, 2024• 3 citations
Publisher

Abstract

Quasi-cyclic low density parity check (QC-LDPC) is widely used in various modern communication standards due to its excellent performance and convenient hardware implementation, but its commonly used pipelined layered decoder faces update conflicts that lead to performance degradation. This letter proposes a shortcut-based decoder to mitigate this problem. When the conflicts occur, we avoid the read/write operations of the log-likelihood ratios (LLRs) and abandon the use of the barrel shifters, and feed those LLRs directly to the next layer. we also attempt to utilize the latest messages for inevitable conflicts. Moreover, the proposed architecture significantly reduces the possibility of conflicts by reordering the base graph matrix (BGM) with a shorter update interval of LLRs, which can achieve maximum utilization in the updated messages. Compared to the state-of-the-art approach in the case of DVB-S2, the proposed architecture can deliver up to 0.25 dB performance gain with faster convergence.

DOI
10.1109/lsp.2024.3362194

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Quasi-cyclic low density parity check (QC-LDPC) is widely used in various modern communication standards due to its excellent performance and convenient hardware implementation, but its commonly used pipelined layered decoder faces update conflicts that lead to performance degradation. This letter proposes a shortcut-based decoder to mitigate this problem. When the conflicts occur, we avoid the read/write operations of the log-likelihood ratios (LLRs) and abandon the use of the barrel shifters, and feed those LLRs directly to the next layer. we also attempt to utilize the latest messages for inevitable conflicts. Moreover, the proposed architecture significantly reduces the possibility of conflicts by reordering the base graph matrix (BGM) with a shorter update interval of LLRs, which can achieve maximum utilization in the updated messages. Compared to the state-of-the-art approach in the case of DVB-S2, the proposed architecture can deliver up to 0.25 dB performance gain with faster convergence.
A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.
Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%-109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.
Pipelined layered decoder (PLD) of quasi-cyclic low-density parity-check (QC-LDPC) codes is one of most popular high-throughput decoder in modern communication systems. However, the traditional QC-LDPC codes are not suitable for PLD and lead to memory access conflict problems (MACPs) that reduce the throughput of PLD. Therefore, an efficient layered block progressive edge-growth (EL-BPEG) algorithm is proposed to construct a class of QC-LDPC codes that can avoid MACPs and increase throughput. EL-BPEG appends check nodes, rather than variable nodes, progressively into Tanner Graph with strict concentrated check-node degrees. And it establishes edges according to the latency of the pipelines in PLD; thus, all idle clocks can be eliminated for the PLD with EL-BPEG codes. Result indicates that the throughput of PLD can be improved by 50.2% to 99.2% by using the EL-BPEG codes compared with the traditional QC-LDPC codes. Simulations show that the error performances of EL-BPEG codes are as well as the codes in standards.
For multi-edge type quasi-cyclic low-density parity-check (MET-QC-LDPC) codes, the presence of common variable nodes shared between rows within a single layer poses great challenges for the hardware design of the decoder. In this study, a cross-layer update scheduling method for pipelined layered MET-QC-LDPC codes is proposed to achieve improved conflict resolution. Through a probabilistic analysis, we show that by pairing layers with relatively small common degrees and performing alternating updates between the paired layers, better conflict resolution can be achieved than the layer-by-layer updating approach. Experimental results demonstrate that, at medium to low code rates, 50% to 75% of memory conflicts can be mitigated through the proposed cross-layer scheduling compared to the layer-by-layer scheduling approach, without compromising decoding performance.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code (280,176) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of 10−2, the decoder outperforms the shorter reference codes (60,40) and (96,64), with an Eb/N0 gain of up to 0.9 dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of 218.62 MHz, resulting in a throughput of 155.77 Mbps, while maintaining a decoding latency of only 1.129 µs and a power consumption of 0.201 W.