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IEEE International Conference on Communication Technology (ICCT)

A QC-LDPC construction algorithm for increasing the throughput of layered decoders

Jianjun Zhang, Mingke Dong, Ye Jin

Published Nov 1, 2013• 2 citations
Publisher

Abstract

Pipelined layered decoder (PLD) of quasi-cyclic low-density parity-check (QC-LDPC) codes is one of most popular high-throughput decoder in modern communication systems. However, the traditional QC-LDPC codes are not suitable for PLD and lead to memory access conflict problems (MACPs) that reduce the throughput of PLD. Therefore, an efficient layered block progressive edge-growth (EL-BPEG) algorithm is proposed to construct a class of QC-LDPC codes that can avoid MACPs and increase throughput. EL-BPEG appends check nodes, rather than variable nodes, progressively into Tanner Graph with strict concentrated check-node degrees. And it establishes edges according to the latency of the pipelines in PLD; thus, all idle clocks can be eliminated for the PLD with EL-BPEG codes. Result indicates that the throughput of PLD can be improved by 50.2% to 99.2% by using the EL-BPEG codes compared with the traditional QC-LDPC codes. Simulations show that the error performances of EL-BPEG codes are as well as the codes in standards.

DOI
10.1109/icct.2013.6820446

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Pipelined layered decoder (PLD) of quasi-cyclic low-density parity-check (QC-LDPC) codes is one of most popular high-throughput decoder in modern communication systems. However, the traditional QC-LDPC codes are not suitable for PLD and lead to memory access conflict problems (MACPs) that reduce the throughput of PLD. Therefore, an efficient layered block progressive edge-growth (EL-BPEG) algorithm is proposed to construct a class of QC-LDPC codes that can avoid MACPs and increase throughput. EL-BPEG appends check nodes, rather than variable nodes, progressively into Tanner Graph with strict concentrated check-node degrees. And it establishes edges according to the latency of the pipelines in PLD; thus, all idle clocks can be eliminated for the PLD with EL-BPEG codes. Result indicates that the throughput of PLD can be improved by 50.2% to 99.2% by using the EL-BPEG codes compared with the traditional QC-LDPC codes. Simulations show that the error performances of EL-BPEG codes are as well as the codes in standards.
A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.
For multi-edge type quasi-cyclic low-density parity-check (MET-QC-LDPC) codes, the presence of common variable nodes shared between rows within a single layer poses great challenges for the hardware design of the decoder. In this study, a cross-layer update scheduling method for pipelined layered MET-QC-LDPC codes is proposed to achieve improved conflict resolution. Through a probabilistic analysis, we show that by pairing layers with relatively small common degrees and performing alternating updates between the paired layers, better conflict resolution can be achieved than the layer-by-layer updating approach. Experimental results demonstrate that, at medium to low code rates, 50% to 75% of memory conflicts can be mitigated through the proposed cross-layer scheduling compared to the layer-by-layer scheduling approach, without compromising decoding performance.
Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%-109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.
In this paper, we propose an optimized belief propagation (OBP) based progressive edge-growth (PEG) method for constructing quasi-cyclic low density parity check (QC-LDPC) codes. In this proposed method, Tanner graphs are built by progressively appending the check nodes rather than the variable nodes. Moreover, this OBP-PEG method considers three new constraint conditions to select the QC-LDPC code sets constructed by the PEG method. Compared with the PEG-based QC-LDPC decoders, the proposed OBP-PEG decoders decrease the number of the input ports of check-node processer by up to 25%, accelerates the convergence speed by up to 11.7% in layered decoding process, and improves the success probability by up to ten times in constructing fast-convergence QC-LDPC codes.
Short cycles in the Tanner graph of a given LDPC code has negative effect on the performance of iterative decoding. To improve the performance, we presented an approach for constructing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes whose associated Tanner graph has large girth and a small amount of short cycles. Each column block of the parity check matrix was designed by adding circulant permutation sub-matrices one after another, provided the current parity check matrix has minimal number of short cycles. The condition for the proposed QC-LDPC codes to have girth at least 6 was also analyzed. Regular and irregular QC-LDPC codes with various lengths and rates can be constructed. Simulations show that the proposed QC-LDPC codes have less short cycles and better performance than existing progressive edge growth based QC-LDPC codes.
In this paper, design of a high throughput low-density parity-check (LDPC) decoder using overlapped message passing scheduling algorithm is presented. Regular hierarchical quasi-cyclic (H-QC) LDPC code is used in this design to provide good coding performance at long code length. The two-level regular H-QC LDPC code matrix structure is exploited to parallelize the row and column decoding operations. Our scheduling algorithm re-arranges these operations across iteration boundaries to avoid memory access conflicts. The memory requirement is reduced by half compared to pipelined decoders without scheduling. A (12288, 6144) LDPC decoder implemented in FPGA achieves 298 Mbps throughput performance.