The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process.
The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process.
Ferroelectric Superconducting Quantum Interference Devices (Fe-SQUIDs) have recently gained attention as a transformative technology for superconducting computing, offering voltage-controlled switching that is essential for large-scale digital circuits. This unique technology has the potential to drive advancements in cryogenic computing by enabling scalable memory systems and voltage-controlled logic circuits. These innovations are critical for the realization of large-scale quantum computers and hold significant promise for high-performance computing and space exploration. In this article, we explore how Fe-SQUIDs, integrated with heater cryotrons (hTrons), can be harnessed to develop key components of computing systems. These include non-volatile memory, voltage-controlled logic circuits, in-memory matrix-vector multiplication systems, and ternary content-addressable memory. We also examine how changes in the key characteristics of Fe-SQUIDs and hTrons influence the performance of these applications, providing insights into the design and optimization of next-generation superconducting hardware.
The growing demand for ultra low power computing and the emergence of quantum technologies have intensified interest in cryogenic electronics, particularly superconducting devices. Despite their promise, current controlled superconducting components face fundamental challenges in cascadability, limiting their effectiveness in complex logic architectures. To overcome this, recent efforts have focused on developing gate tunable superconducting devices, such as Josephson junction field effect transistors (JJFETs). However, achieving robust control and sufficient supercurrent gain, both critical for transistor-like performance in logic circuits remains a key challenge. A recent advancement in JJFET design, based on InAs and GaSb heterostructures, demonstrates enhanced gain and favorable device characteristics suitable for circuit integration. Building on this innovation, we propose and analyze fundamental voltage controlled logic topologies using the quantum enhanced JJFET. We develop a Verilog A based circuit compatible compact model of the quantum enhanced JJFET which accurately captures the experimentally observed device characteristics. To ensure cascadability, our logic circuits incorporate the multilayered Heater Nanocryotron (nTron), a superconducting nanowire-based thermal switch. Through simulation based analysis, we demonstrate the successful implementation of fundamental logic gates, including NOT, NAND, and NOR. Furthermore, we design a 3 input majority gate, which plays a pivotal role in quantum and reversible computing due to its universality. Finally, to demonstrate the cascadability of our proposed logic topology, we demonstrate the operation of a 2 input XOR gate based on our designed JJFET based NOT, NAND, and NOR gate.
Cryogenic (cryo) memory devices, designed to operate at/below 4 Kelvin (K) temperature, is a prime enabler of practical quantum computing systems, and superconducting (SC) electronic platforms (Figs. 1(a), (b)) [1]. The state-of-the-art quantum algorithms require many arbitrary rotations which demand a large memory to store program instructions [2]. SC qubits (used in most of the existing quantum computing systems) are highly sensitive to noise and hence, to protect the qubit states from thermal disturbances, they are placed at a few milli-Kelvin (mK) temperature. Furthermore, to preserve the integrity of the quantum states, the SC qubits undergo continuous error correction schemes, requiring extensive memory and bandwidth [2]. Superconducting electronics (SCE) (targeted towards space applications, and high-performance computing) outperforms the conventional CMOS counterparts in terms of speed and energy-efficiency (Fig. 1(c)) [3]. Decades of research efforts have given rise to three major categories (and several sub-variants) of cryo-memories based on SC, non-SC, and hybrid technologies (Fig. 2) [2], [4]–[6]. However, the existing variants suffer from one or more of the following challenges - (i) limited scalability, (ii) process complexity, (iii) bulky peripherals, (iv) array-level interference, (v) volatility, and (vi) speed incompatibility. Therefore, a scalable cryo-memory system remains elusive. To address these existing issues, here, we present a novel cryo-memory system utilizing -(i) the polarization-induced Cooper-pair [7] modulation in a ferroelectric(FE)superconducting quantum interference device (SQUID) (Fig. 3(a)) [8], and (ii) current controlledSC↔non−SCswitching in a heater cryotron(hTron)(Fig. 4) [4]. Discrete prototypes of these devices have been demonstrated recently, but their coupled interactions (which we harness in our work) were never explored before.
Superconductivity serves as a unique solid-state platform for electron interference at a device-relevant lengthscale, which is essential for quantum information and sensing technologies. As opposed to semiconducting transistors that are operated by voltage biasing at the nanometer scale, superconductive quantum devices cannot sustain voltage and are operated with magnetic fields, which impose a large device footprint, hindering miniaturization and scalability. Here, we introduce a system of superconducting materials and devices that have a common interface with a ferroelectric layer. An amorphous superconductor was chosen for reducing substrate-induced misfit strain and for allowing low-temperature growth. The common quantum pseudowavefunction of the superconducting electrons was controlled by the nonvolatile switchable polarization of the ferroelectric by means of voltage biasing. A controllable change of 21% in the critical temperature was demonstrated for a continuous film geometry. Moreover, a controllable change of 54% in the switching current of a superconducting quantum interference device was demonstrated. The ability to voltage bias superconducting devices together with the nonvolatile nature of this system paves the way to quantum-based memory devices.
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
Cryogenic (cryo) memory blocks are envisioned to be crucial components for - (i) scalable quantum computing systems with> 1000 qubits [1], and (ii) superconducting (SC) single flux quantum (SFQ) systems [2]. Decades of research has led to a whole host of cryo-memory variants (SC, non-SC, and hybrid), and more are being actively explored. Despite having such massive interest in the search for cryo-storage solutions, the design possibilities for compatible sense amplifiers (SA) remain largely unexplored. The existing approaches for cryogenic sensing are mostly agnostic to the unique properties of the memory array [3]–[5]. For example, the recently proposed SC and twistronic memories promise seamless compatibility with the cryogenic processors in terms of speed, power, and temperature range [4]–[7]. However, they rely on current-driven read operation, and necessitate voltage-based sensing. Therefore, a current-based cryo-SA [3] cannot be used for these emerging cryo-memory variants. In this work, we propose a voltage sense amplifier (VSA) for cryogenic memories utilizing the Josephson junction field effect transistor (JJFET) [8] as the primary component, and the heater cryotron (hTron) [4], [9] as an auxiliary entity. We exploit their coupled interactions to sense ultra-low (< 1 mV) voltage difference (customary for many cryo-memory technologies [4]–[7]) between the binary memory states (0/1) at/below 4 Kelvin temperature.