We propose a fully pipelined Quantum-Classical interface (QC-IF) architecture for fault-tolerant quantum computing. The current Quantum-Classical interface has been working for superconducting quantum computers with 64 qubits in RIKEN and 16 qubits in QIQB Osaka University. The interface sends/receives a sequence of pulses to/from the qubits and demodulates the acquired ones, in which a batch controller is designed to operate up to 500 milliseconds, longer than the coherence time. For Fault-Tolerant Quantum Computers(FTQC), however, a fully pipelined Quantum-Classical Interface is required to send and receive pulses, collecting syndrome information over time far beyond the coherence time. Here, we present a control plane newly incorporated into the current architecture to handle consecutive sending, receiving, and demodulating pulses. Since the current system has achieved wire-rate operation to retrieve and transmit signals, the control plane for continuous operation naturally extends the system to a fully pipelined architecture.
We propose a fully pipelined Quantum-Classical interface (QC-IF) architecture for fault-tolerant quantum computing. The current Quantum-Classical interface has been working for superconducting quantum computers with 64 qubits in RIKEN and 16 qubits in QIQB Osaka University. The interface sends/receives a sequence of pulses to/from the qubits and demodulates the acquired ones, in which a batch controller is designed to operate up to 500 milliseconds, longer than the coherence time. For Fault-Tolerant Quantum Computers(FTQC), however, a fully pipelined Quantum-Classical Interface is required to send and receive pulses, collecting syndrome information over time far beyond the coherence time. Here, we present a control plane newly incorporated into the current architecture to handle consecutive sending, receiving, and demodulating pulses. Since the current system has achieved wire-rate operation to retrieve and transmit signals, the control plane for continuous operation naturally extends the system to a fully pipelined architecture.
Fault tolerance is an indispensable prerequisite for constructing large-scale universal quantum computers. Drawing philosophies from classical computer architecture, this paper presents a hardware-agnostic three-layer high-level architectural framework for generic fault-tolerant quantum computation. Guided by the real execution workflows of fault-tolerant quantum algorithms, the proposed model is decoupled from specific physical qubit hardware platforms and quantum error correction codes, serving as a universal abstract standard rather than a platform-specific implementation scheme. Special attention is devoted to the intermediate Fault-Tolerance Layer, which serves as the architectural bridge between application-level logical programs and hardware-level execution. We systematically characterize its five internal components, the interfaces and data exchanged among them, and the execution, correction, and adaptation paths that together enable logical synthesis, fault-tolerant resources management, decoding, and runtime fault-tolerant control. An end-to-end example is further provided to illustrate the full-stack operating pipeline of fault-tolerant quantum algorithms under this framework. Given the increasing emphasis on modular, heterogeneous, and cross-layer fault-tolerant quantum systems, our architecture provides a unified foundational model for organizing such designs.
Scaling fault-tolerant quantum computing (FTQC) requires orchestrating millions of operations continuously across a tightly coupled classical-quantum control stack. A critical challenge in this orchestration is determining the optimal hardware-software boundary, i.e., the Quantum Instruction Set Architecture (QISA). We focus on cryogenic, fixed-connectivity qubit platforms, such as superconducting and topological Majorana qubits. For these, existing QISA choices either operate at too low a level, violating cryogenic thermal budgets at scale, or at too high a level, imposing unrealizable complexity on the control engine. To reason about these tradeoffs, we introduce the ARIES instruction set hierarchy, which categorizes QISAs into distinct abstraction levels. To systematically evaluate these levels, we develop an end-to-end evaluation toolflow featuring a cycle-accurate classical driver and hardware engine simulator. Using eight quantum applications across superconducting and topological qubit platforms, we measure instruction bandwidth, transceiver power dissipation, and measurement processing overheads. We demonstrate that while physical-level abstractions exceed the thermal limits of dilution refrigerators by orders of magnitude, canonical-level abstractions significantly underestimate hardware routing congestion and execution runtimes. Our Level 4 QISA (local logical operations) offers an optimal architectural balance. As quantum hardware platforms scale toward FTQC in the coming years, our findings provide concrete architectural guidance for the design of their classical control stacks and instruction interfaces.
Abstract Fault-tolerant quantum computing requires a classical control stack that can decode syndrome data within the coherence time of physical qubits. We address this requirement for a single-logical-qubit space-time repetition-code memory, treating the classical–quantum interface as a distributed real-time systems problem. The proposed architecture combines software Pauli frame tracking with a pipelined, streaming decoder mapped directly to FPGA hardware. Operating over a space-time syndrome graph, the system separates data-qubit errors from measurement ancilla faults. We evaluate Greedy, Minimum-Weight Perfect Matching (MWPM), and Union-Find (UF) decoders under a depolarizing noise model (effective bit-flip rate pX = 2p/3) with phenomenological measurement faults. A first Monte Carlo framework was implemented for distances d = 3, 5, and 7. Publication-grade threshold crossings were not obtained in the present shot budget; reported p_th figures below are literature-aligned design targets, not crossings measured in this work. Prior published comparisons motivate pth(MWPM) ≈ 10.4% and pth(UF) ≈ 9.6%, as an expected algorithmic penalty ∆ ≈ 0.8% that remains well within operational margins. A 400 MHz pipeline schedule targets deterministic execution between 170ns and 390ns at 400MHz on an AMD Zynq UltraScale+ RFSoC, satisfying sub-microsecond round-trip deadlines. Mitigation protocols for pipeline backpressure, queue overruns, and frame corruption are established to ensure deterministic runtime stability. Index Terms— quantum error correction, real-time systems, FPGA, Union-Find decoding, minimum-weight perfect matching, Pauli frame.
Fault-tolerant quantum computation requires the coordinated action of three distinct systems: classical control logic, quantum hardware, and classical error decoders. Current scheduling models treat logical operations as atomic, hiding the fact that these subsystems operate sequentially and spend significant time idle. We present a pipelined execution framework that decomposes each logical operation into its component stages i.e. Control, Execute, and Decode. Building on this, we discuss some speculation strategies that allow successor operations to begin processing before their predecessors have completed decoding. We evaluate our framework on several common benchmarks and show that pipelining with speculation reduces total pipeline steps by 20-40% compared to a no-speculation baseline. The most aggressive strategy consistently outperforms conservative alternatives, even though partial rollback is needed at times, because the per-rollback penalty is small relative to the parallelism gained. We further show that speculation facilitates load balancing by distributing work more evenly across the heterogeneous subsystems of a fault-tolerant quantum computer, converting idle time into useful computation while also saving on execution time.
Quantum computers are expected to drastically accelerate certain computing tasks versus classical computers. Noisy intermediate-scale quantum (NISQ) devices, which have tens to hundreds of noisy physical qubits, are gradually becoming available, but it is still challenging to achieve useful quantum advantages in meaningful tasks. On the other hand, full fault-tolerant quantum computing (FTQC) based on quantum error correction code remains far beyond realization due to its extremely large requirement of high-precision physical qubits. In this study, we propose a quantum computing architecture to close the gap between NISQ and FTQC architectures. Our architecture is based on erroneous arbitrary rotation gates and error-corrected Clifford gates implemented by lattice surgery. We omit the typical distillation protocol to achieve direct analog rotations and small qubit requirements, and minimize the remnant errors of the rotations by a carefully designed state injection protocol. Our estimation based on numerical simulations shows that for early-FTQC devices that consist of 104 physical qubits with physical error probability p=10−4 , we can perform roughly 1.72×107 Clifford operations and 3.75×104 arbitrary rotations on 64 logical qubits. Such computations cannot be realized by the existing NISQ and FTQC architectures on the same device, as well as classical computers. We hope that our proposal and the corresponding development of quantum algorithms based on it will bring new insights into the realization of practical quantum computers in the future. Published by the American Physical Society 2024
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.