Next generation of quantum computers calls for reduced dc power dissipation of the cryogenic low‐noise amplifier (LNA) applied in reading out the superconducting qubits. This article reports on processing and evaluation of a 100‐nm gate length indium phosphide high electron mobility transistor (InP HEMT) technology used in the design of such LNAs. InP HEMTs with size of 4 × 50 µm were measured on‐wafer by DC and S‐parameter characterization. Device noise performance was indirectly evaluated by measuring and modeling the gain and noise of a three‐stage hybrid 4–8 GHz cryogenic LNA equipped with the InP HEMTs. When operating the LNA at a DC power of 2.1 mW, the InP HEMT LNA average noise temperature was 1.4 K with an average gain of 41.6 dB. The minimum noise temperature of the InP HEMT was estimated to be 1.1 K at 6 GHz. The performance achieved for the InP HEMT LNA is comparable to the LNAs currently used in quantum computing while requiring only 27% of the DC power consumption. Small‐signal modeling of the InP HEMT suggested that this was due to a low output conductance associated with a large gate‐recess length used in device fabrication.
High-fidelity single-shot readout of superconducting qubits is essential for fault-tolerant quantum computation. Without a quantum-limited amplifier such as a Josephson parametric amplifier, the cryogenic high-electron-mobility-transistor (HEMT) low-noise amplifier (LNA) at the 4 K stage is the dominant noise source in the readout chain. HEMT LNAs are conventionally characterized by Y-factor measurements of the noise temperature
TN, independently of the quantum measurement they ultimately serve. Here we present a qubit-in-the-loop benchmarking method. The method uses the two-dimensional IQ histogram of single-shot readout as a direct figure of merit. We apply it to three state-of-the-art cryogenic InP HEMT LNAs with 53\%, 60\%, and 70\% channel indium content, together with a commercial reference amplifier. The 60\% and 70\% devices have similar
TN in Y-factor measurements, both lower than the 53\% device. The 70\% device has the highest gain, but qubit readout SNR and assignment fidelity
Fa instead peak at 60\%. Using this method, we map
Fa against HEMT LNA dc power consumption for each device.
Fa does not simply saturate with increasing power. For several devices it declines above a device-dependent power well below typical operating points. For the 60\% device, which has the highest overall
Fa, about 1~mW is needed to maintain
Fa>85%. Across all four devices,
Fa>80% is reached with as little as about 0.3~mW, roughly an order of magnitude below typical operating points. These results establish a qubit-referenced benchmarking methodology and provide practical guidance for amplifier selection and bias in power-constrained multi-qubit readout systems.
The cryogenic indium phosphide (InP) high-electron-mobility transistor (HEMT) low-noise amplifier (LNA) is used for the readout amplification of qubits at
4K where cooling capabilities are limited implying that the dc power of the active circuits is an essential design constraint. In this article, the RF and noise performance of the InP HEMT under ultralow-power (ULP) operation at
4K has been characterized. The small-signal and noise parameter model of the InP HEMT was extracted down to 1
μW. The tradeoff between noise performance and dc power consumption was analyzed in terms of the drain current and drain voltage. A 4–6 GHz hybrid cryogenic HEMT LNA designed for qubit readout and optimized for lowest noise below
1mW dc power consumption was fabricated. The measured performance of the LNA at
4K attained 23.1 dB average gain and 2.0 K average noise temperature at 200
μW dc power.
Large-scale qubit readout in quantum computing systems requires highly sensitive amplification with minimal power consumption to reduce the thermal load and preserve qubit integrity. We propose a pulse-operated cryogenic low-noise amplifier (LNA) scheme that minimizes the influence of the LNA on qubit operation and reduces power consumption by duty cycling. A modified commercially available cryogenic hybrid LNA based on InP high-electron mobility transistors (HEMTs) has been characterized to demonstrate the feasibility of pulsed operation for qubit readout. The transient noise and gain performance of the LNA were obtained through a cryogenic time domain noise measurement setup with 5-ns time resolution and a measured noise standard deviation (SD) below 0.3 K. The time-domain noise and gain performance of the LNA in response to a square gate voltage waveform were investigated. Through an analysis of the LNA’s recovery limitations, we developed a fast recovery bias strategy leading to the optimization of the gate voltage waveform using a genetic algorithm (GA). This resulted in a strong enhancement of transient noise and gain performance with a recovery time of 35 ns. The drain current transients were measured to calculate the average power consumption of the pulse-operated LNA, which confirmed a reduction in average power consumption proportional to the duty cycle. This work contributes to the development of high-performance and low-power amplifier solutions critical for large-scale qubit readout applications.
This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies
0.252mm2. Post-layout simulations confirm input/output S-parameter matching better than
−10dB,41−44dBgain with
<3dBripple,
<5Knoise temperature across
4−9GHz, and a worst-case OP1 dB compression point of
−19.96.6dBm. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.
Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNAs) for qubit readout. Here we presented a C-band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on a 150 nm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance matching to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third stages enhances the overall stability. Moreover, the pHEMT self-bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only a single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a minimum noise temperature of 4 K and an average gain of 40 dB. We further benchmarked this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.