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Applied Physics Letters

300 mm CMOS-compatible superconducting HfN and ZrN thin films for quantum applications

Roman Potjan, Marcus Wislicenus, Oliver Ostien, Raik Hoffmann, Maximilian Lederer, André Reck, Jennifer Emara, Lisa Roy, Benjamin Uhlig, J. Wosnitza

Published Oct 23, 2023• 15 citations
Publisher

Abstract

The rising interest in increased manufacturing maturity of quantum processing units is pushing the development of alternative superconducting materials for semiconductor fab process technology. However, these are often facing CMOS process incompatibility. In contrast to common CMOS materials, such as Al, TiN, and TaN, reports on the superconductivity of other suitable transition-metal nitrides are scarce, despite potential superiority. Here, we demonstrate fully CMOS-compatible fabrication of HfN and ZrN thin films on state-of-the-art 300 mm semiconductor process equipment, utilizing reactive DC magnetron sputtering on silicon wafers. Measurement of mechanical stress and surface roughness of the thin films demonstrates process compatibility. We investigated the materials phase and stoichiometry by structural analysis. The HfN and ZrN samples exhibit superconducting phase transitions with critical temperatures up to 5.84 and 7.32 K, critical fields of 1.73 and 6.40 T, and coherence lengths of 14 and 7 nm, respectively. A decrease in the critical temperature with decreasing film thickness indicates mesoscopic behavior due to geometric and grain-size limitations. The results promise a scalable application of HfN and ZrN in quantum computing and related fields.

DOI
10.1063/5.0176060

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The rising interest in increased manufacturing maturity of quantum processing units is pushing the development of alternative superconducting materials for semiconductor fab process technology. However, these are often facing CMOS process incompatibility. In contrast to common CMOS materials, such as Al, TiN, and TaN, reports on the superconductivity of other suitable transition-metal nitrides are scarce, despite potential superiority. Here, we demonstrate fully CMOS-compatible fabrication of HfN and ZrN thin films on state-of-the-art 300 mm semiconductor process equipment, utilizing reactive DC magnetron sputtering on silicon wafers. Measurement of mechanical stress and surface roughness of the thin films demonstrates process compatibility. We investigated the materials phase and stoichiometry by structural analysis. The HfN and ZrN samples exhibit superconducting phase transitions with critical temperatures up to 5.84 and 7.32 K, critical fields of 1.73 and 6.40 T, and coherence lengths of 14 and 7 nm, respectively. A decrease in the critical temperature with decreasing film thickness indicates mesoscopic behavior due to geometric and grain-size limitations. The results promise a scalable application of HfN and ZrN in quantum computing and related fields.
We report a milestone in achieving large-scale, ultrathin (~5 nm) superconducting NbN thin films on 300 mm Si wafers using a high-volume manufacturing (HVM) industrial physical vapor deposition (PVD) system. The NbN thin films possess remarkable structural uniformity and consistently high superconducting quality across the entire 300 mm Si wafer, by incorporating an AlN buffer layer. High-resolution X-ray diffraction and transmission electron microscopy analyses unveiled enhanced crystallinity of (111)-oriented δ-phase NbN with the AlN buffer layer. Notably, NbN films deposited on AlN-buffered Si substrates exhibited a significantly elevated superconducting critical temperature (~2 K higher for the 10 nm NbN) and a higher upper critical magnetic field or Hc2 (34.06 T boost in Hc2 for the 50 nm NbN) in comparison with those without AlN. These findings present a promising pathway for the integration of quantum-grade superconducting NbN films with the existing 300 mm CMOS Si platform for quantum information applications.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Abstract In this paper, we investigate the superconducting critical temperature, morphology and structural properties of NbN ultra-thin films (5–7 nm) deposited by reactive sputtering on top of silicon nitride (SiN) over 200 mm silicon wafers. We demonstrate the effectiveness of a 10 nm thick spacer layer of AlN in raising the superconducting critical temperature from 5.0 K to 7.2 K and from 7.3 K to 9.3 K for 5 nm and 7 nm NbN thickness respectively. By combining investigations with x-ray diffraction and transmission electron microscopy, we highlight significant modifications of the crystalline properties of the NbN film on top of the AlN spacer layer. When directly deposited on SiN, the grains of the NbN polycrystalline layer are randomly oriented. In contrast, when deposited on top of the AlN (0001) spacer layer, the NbN layer is textured along the (111) direction, leading to increased critical temperatures. As AlN is a CMOS-compatible material, these findings are particularly relevant in view of the future integration of high-performance superconducting nanowire single photon detectors on large-scale quantum photonic chips.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1, 2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Low-Temperature Stabilization of δδδ-NbN Superconducting Thin Films through Energy-Selective Ion Beam Sputtering
Achieving high-quality superconducting thin films at low temperatures is a central challenge for scalable quantum device integration and Complementary Metal-Oxide-Semiconductor (CMOS)-compatible fabrication. Here, we demonstrate a room-temperature magnetron sputtering approach for synthesizing niobium nitride (NbN) thin films using a novel energy-selective ion source that enables independent control of ion energy and ion flux. This capability provides a powerful route to precisely tailor surface kinetics and crystallization pathways, overcoming longstanding limitations in stabilizing high-quality NbN at reduced temperatures. The resulting films were characterized by superconducting transport measurements, X-ray diffraction, X-ray photoelectron spectroscopy, and transmission electron microscopy. Compared with conventional reactive sputtering, ion beam-assisted growth yields a substantial narrowing of the transition width at the superconducting temperature, indicating improved phase purity and electronic homogeneity. Furthermore, this work introduces energy-selective ion control as a general, non-equilibrium route to stabilize metastable superconducting phases at low temperatures, offering a new design paradigm for thin-film quantum materials.
The interplay of alternative materials, large-scale integration technologies, and innovative devices plays a pivotal role on the way to fault-tolerant quantum computing. In this context, gate-controlled superconductivity (GCS) emerges as a key enabling technology, promising to advance superconducting logic and quantum electronics, complementing conventional approaches based on Josephson effects and quantum interference. Here, we demonstrate all-metallic superconducting ZrN nanostructures on silicon, fabricated entirely using a subtractive, monolithic dry-etch approach with a 300 mm CMOS-compatible process flow. For Dayem-bridge weak links with decreasing width down to 27 nm, we observe Tc of 7.3 K, width-dependent switching characteristics, and a progressive approach of the tunneling limit. In laterally gated Dayem-bridge and nanowire devices, we observe GCS with full suppression of the critical current, where required gate voltages <5 V promise compatibility with CMOS interfaces. Asymmetries in polarity-dependent power injection via field emission support GCS models that attribute the effect to quasiparticle relaxation through phonon emission. Additional asymmetries in the GCS effect suggest an influence of the substrate condition after dry etching. Field emission features in the gated nanowire device imply superimposed current paths along the gate edge and corners. Finally, we analyze magnetic interference in Dayem-bridge weak links and superconducting quantum interference devices, where quantum interference is governed by Josephson effects and inductance loop asymmetries. Our results contribute to the scaling efforts in hybrid superconducting electronics and quantum-processing units.