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ACM Conference on Research in Adaptive and Convergent Systems (RACS)

Towards Scalable Quantum Circuit Simulation via RDMA

Chia-Hsin Hsu, Chuan-Chi Wang, Nai-Wei Hsu, Chia-Heng Tu, Shih‐Hao Hung

Published Aug 6, 2023• 4 citations
Publisher

Abstract

The trend towards optimization of quantum circuit simulators (QCS) has been driven by the rapid development of quantum computing, as there is a growing interest in creating high-efficiency QCS for quantum computing systems and applications. Despite this growth, the existing classical simulators pose challenges in simulating large quantum operations due to the exponential growth of memory and computation resources required. To overcome these issues, some studies have explored the use of non-volatile memory, such as solid-state disks (SSDs), to store a large amount of state vector while maintaining cost efficiency. However, such highly frequent read-and-write operations in large quantum simulations can quickly deplete the lifespan of SSDs, leading to overestimated practical efficiency and environmental concerns. Alternatively, Remote Direct Memory Access (RDMA) can be used to expand memory capacity, allowing computers in a network to access remote memories with low latency and high bandwidth. Therefore, we propose using one-sided RDMA operations along with a series of optimizations to expand memory capacity and efficiently maximize the utilization of unused memory assets. The experimental results demonstrate that our approaches can be practically scaled up without any lifespan consumption. The proposed optimization can get a 3.0x speedup compared to the local memory approach and a maximum speedup of 2.0x compared to the naive RDMA-based approach, as observed in our benchmark test.

DOI
10.1145/3599957.3606215

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The trend towards optimization of quantum circuit simulators (QCS) has been driven by the rapid development of quantum computing, as there is a growing interest in creating high-efficiency QCS for quantum computing systems and applications. Despite this growth, the existing classical simulators pose challenges in simulating large quantum operations due to the exponential growth of memory and computation resources required. To overcome these issues, some studies have explored the use of non-volatile memory, such as solid-state disks (SSDs), to store a large amount of state vector while maintaining cost efficiency. However, such highly frequent read-and-write operations in large quantum simulations can quickly deplete the lifespan of SSDs, leading to overestimated practical efficiency and environmental concerns. Alternatively, Remote Direct Memory Access (RDMA) can be used to expand memory capacity, allowing computers in a network to access remote memories with low latency and high bandwidth. Therefore, we propose using one-sided RDMA operations along with a series of optimizations to expand memory capacity and efficiently maximize the utilization of unused memory assets. The experimental results demonstrate that our approaches can be practically scaled up without any lifespan consumption. The proposed optimization can get a 3.0x speedup compared to the local memory approach and a maximum speedup of 2.0x compared to the naive RDMA-based approach, as observed in our benchmark test.
Quantum circuit simulation is essential for researchers to develop and evaluate novel quantum algorithms with classical computers. Although full-state quantum circuit simulations are widely utilized for prototyping and debugging, they are computationally intensive due to the exponential growth in simulation time as the system size grows. To address the performance bottlenecks associated with conventional gate-by-gate simulation, this work refines the block-by-block simulation paradigm through blocking optimization, taking into account the architectural characteristics of hardware. The primary contribution of this research is the gate block search algorithm (GBSA), which efficiently groups the maximum number of quantum gates into gate blocks. This grouping technique enhances data reuse and reduces redundant memory accesses and I/O overhead during gate application. The proposed method is evaluated using both gate-level and circuit-level benchmarks on an AMD 64-core processor. Compared to conventional gate-by-gate simulators, such as QuEST and AerSimulator, the proposed approach achieves up to a 4.7× speedup in CPU execution and a 2.9× speedup in SSD-based scenarios. Furthermore, it can lead to a remarkable 46× reduction in memory and I/O traffic. These results indicate that the proposed block-based simulation strategy substantially improves the efficiency of quantum circuit simulation and can be readily adapted to multi-device environments, thereby supporting the rapid development of next-generation quantum algorithms.
Quantum circuit simulation (QCS) is essential in the noisy intermediate scale quantum (NISQ) era when real quantum computers are scarce. However, fully tracking the states of a quantum system in QCS is highly challenging due to the exponential memory growth that significantly limits the computational reach of classical systems for QCS. Though it is straightforward to leverage secondary storage to extend the scale of QCS, excessive data movement between memory and storage dominates the simulation time, making this solution unrealistic. To tackle this challenge, we identify an intrinsic property of QCS and implement an open-source framework to effectively reduce data movement by >116x. We evaluate the framework on various benchmarks and demonstrate 4x memory reduction with only <20% overhead. On a memory constrained system, we show that it extends the scale of QCS to 32 qubits (64 GB memory requirement) while existing simulators are bounded to 28 qubits (4 GB memory requirement). Our implementation can be accessed via https://github.com/Zhaoyilunnn/qdao.
Quantum computing is a rapidly expanding field with applications ranging from optimization all the way to complex machine learning tasks. Quantum memories, while lacking in practical quantum computers, have the potential to bring quantum advantage. In quantum machine learning applications for example, a quantum memory can simplify the data loading process and potentially accelerate the learning task. Quantum memory can also store intermediate quantum state of qubits that can be reused for computation. However, the depth, gate count and compilation time of quantum memories such as, Quantum Read Only Memory (QROM) scale exponentially with the number of address lines making them impractical in state-of-the-art Noisy Intermediate-Scale Quantum (NISQ) computers beyond 4-bit addresses. In this paper, we propose techniques such as, pre-decoding logic and qubit reset to reduce the depth and gate count of QROM circuits to target wider address ranges such as, 8-bits. The proposed approach reduces the number of gates and depth count by at least 2X compared to the naive implementation at only 36% qubit overhead. A reduction in circuit depth and gate count as high as 75X and compilation time by 85X at the cost of a maximum of 2.28X qubit overhead is observed. Experimentally, the fidelity with the proposed pre-decoding circuit compared to existing optimization approach is also higher (as much as 73% compared to 40.8%) under reduced error rates.
Quantum computing has shown great potential in addressing traditional computational challenges, but due to its high error rates and noise issues, classical simulation has become an essential tool for verifying its performance. However, the superposition and entanglement properties of quantum systems pose significant challenges for simulation, especially when memory is limited. Although circuit cutting methods can decompose large-scale quantum circuits into smaller computational tasks to reduce computational load, previous research primarily focused on their application to quantum computers, without fully considering their effectiveness in quantum circuit simulation. This study fills that gap by proposing an optimization scheme based on a heuristic cutting algorithm and subcircuit state vector reuse to address memory limitations in simulations. By incorporating global computational cost considerations and an integer programming model, the heuristic method proposed in this paper not only optimizes the cutting process but also combines subcircuit state vector reuse to reduce redundant calculations and memory usage. Experimental results show that compared to current popular circuit cutting methods, the proposed approach significantly improves simulation speed while reducing memory requirements, effectively addressing the challenges in quantum circuit simulation. The overall average speedup achieved 46%.
Scalable classical simulation of quantum circuits is crucial for advancing quantum algorithm development and validating emerging hardware. This work focuses on performance enhancements through targeted low-level and NUMA-aware tuning on a single-node system, thereby not only advancing the efficiency of classical quantum simulations but also establishing a foundation for scalable, heterogeneous implementations that bridge toward noiseless quantum computing. Although few prior studies have reported similar hardware-level optimizations, such implementations have not been released as open-source software, limiting independent validation and further development. We introduce an open-source, high-performance extension to the QuEST state vector simulator that integrates state-of-the-art low-level and NUMA-aware optimizations for modern processors. Our approach emphasizes locality-aware computation and incorporates hardware-specific techniques including NUMA-aware memory allocation, thread pinning, AVX-512 vectorization, aggressive loop unrolling, and explicit memory prefetching. Experiments demonstrate substantial speedups--5.5-6.5x for single-qubit gate operations, 4.5x for two-qubit gates, 4x for Random Quantum Circuits (RQC), and 1.8x for the Quantum Fourier Transform (QFT). Algorithmic workloads further achieve 4.3-4.6x acceleration for Grover and 2.5x for Shor-like circuits. These results show that systematic, architecture-aware tuning can significantly extend the practical simulation capacity of classical quantum simulators on current hardware.
Quantum Random Access Memory (QRAM) represents a crucial component in the realization of practical quantum computers, enabling fast and probabilistic data access for quantum algorithms. However, accurately simulating QRAM's operation presents a formidable challenge due to the inherent randomness and quantum mechanical nature of the system. This work investigates and proposes novel simulation techniques and optimization algorithms aimed at mitigating this computational complexity. We explore various approaches, including stochastic simulation methods, reduced-order modeling, and tailored optimization strategies, focusing on minimizing the number of quantum operations required for accurate QRAM simulation. The results demonstrate significant reductions in computational cost while maintaining a reasonable level of fidelity, paving the way for more efficient design and analysis of QRAM architectures. The core claim of this research is that the development of QRAM is fundamentally limited by the complexity of its simulation, and this work offers a direct path toward overcoming this bottleneck.