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IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology

H.-L. Chiang, R. A. Hadi, J.-F. Wang, Hung-Chi Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, Wen-Shen Chou, Brian Lien, Yeong‐Hwa Chang, Y.-C. Chen, Y.-H. Wang, T.-C. Chen, J.-C. Liu, Yuhao Liu, Meng‐Hsueh Chiang, Kuo-Hsing Kao, B. Pulicherla, Jun Cai, C. S. Chang, K.-W. Su, K.-L. Cheng, Tzu-Jin Yeh, Yiyun Peng, Christian Enz, Mau-Chung Frank Chang, M.-F. Chang, H.‐S. Philip Wong, Iuliana P. Radu

Published Jun 11, 2023• 10 citations
Publisher

Abstract

Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit $(\sim 0.31 \times)$. Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.

DOI
10.23919/vlsitechnologyandcir57934.2023.10185325

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•Jan 1, 2016•0 citations
Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit (∼0.31×)(\sim 0.31 \times)(∼0.31×). Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
Scaling superconducting quantum computers to the fault-tolerant regime calls for a commensurate scaling of the classical control and readout stack. Today's systems largely rely on room-temperature, rack-based instrumentation connected to dilution-refrigerator cryostats through many coaxial cables. Looking ahead, superconducting fault-tolerant quantum computers (FTQCs) will likely adopt a heterogeneous quantum-classical architecture that places selected electronics at cryogenic stages -- for example, cryo-CMOS at 4~K and superconducting digital logic at 4~K and/or mK stages -- to curb wiring and thermal-load overheads. This review distills key requirements, surveys representative room-temperature and cryogenic approaches, and provides a transparent first-order accounting framework for cryoelectronics. Using an RSA-2048-scale benchmark as a concrete reference point, we illustrate how scaling targets motivate constraints on multiplexing and stage-wise cryogenic power, and discuss implications for functional partitioning across room-temperature electronics, cryo-CMOS, and superconducting logic.
Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.
Surface codes are crucial for fault-tolerant quantum computing (FTQC) and rely on syndrome analysis to identify quantum errors. Superconducting qubits are operating at extremely low temperatures, but the room-temperature syndrome analyzer limits scalability. This paper explores syndrome analysis at an intermediate temperature (around 4 K) and focuses on a hardware-friendly exhaustive search algorithm. Results show that using 4-bit weights enables error correction with a code distance of 5 and a physical error rate of 10−4. The energy consumption per logical qubit per error correction is1.13×10−31.13\times 10^{-3}1.13×10−3nJ, supporting up to 8.86×105\times {10}^{5}×105logical qubits in a cryogenic environment.
Quantum computing promises an exponentially higher computational power than classical computers; although all the building blocks have become available, certain constraints still prevent quantum advantage. The fundamental challenge in building a practical quantum computer is integrating thousands of highly coherent qubits with the control and readout electronics. The need for a high‐coherence qubit drives the effort for quantum error correction algorithms to create fault‐tolerant quantum systems. Error correction becomes tangible in a quantum processor only in large numbers of qubits. Thus, the other challenge is reducing the number of physical interconnects (coaxial lines) between the quantum–classical interface and bulky room‐temperature electronics. To interface thousands of qubits, interconnects can be reduced by bringing the control and readout electronics near the quantum processor. Cryogenic complementary metal–oxide–semiconductor (CMOS) technology has been an ideal candidate for this purpose. Integrated control and readout at cryogenic temperatures require low power dissipation circuit designs and techniques such as frequency‐division multiplexing (FDM) due to the finite cooling power of a dilution refrigerator. Herein, an overview of each building block in a superconducting quantum computer is provided, focusing on scalability. Furthermore, this article is concluded with an outlook discussing current challenges and future directions for the scalable superconducting control and readout.
Recent advances in solid-state qubit technology are paving the way to fault-tolerant quantum computing systems. However, qubit technology is limited by qubit coherence time and the scaling of quantum processors is limited by the complexity of coupling quantum systems with a classical electronic infrastructure. Hence, the proposed approach is to use CMOS at cryogenic temperatures, in order to ensure physical proximity to the quantum bits, thus reducing thermal gradients and increasing compactness. In this thesis, several RF circuits designed using commercial CMOS technology have been shown to be working at cryogenic temperatures. Such circuits could be easily interfaced (or integrated, in the future) with a qubit processor. The performance of the circuits is comparable to the state-of-the-art systems, currently used as control units for qubits. Moreover, these circuits have a much smaller form factor and could be made to work inside a dilution refrigerator where the qubits are operational, hence providing the first demonstration of a scalable solution.