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Institute of Physics eBooks

Quantum fault-tolerant circuits

Hafiz Md. Hasan Babu

Published Jun 1, 2023• 0 citations
Publisher

Abstract

This part of the book describes some background and preliminary studies of quantum fault-tolerant circuits in this chapter. The approach for designing a fault tolerant quantum adder (full-adder) is given in this chapter. A design for a fault tolerant multiplier (signed multiplier) is also shown. Finally, the design procedure for a quantum fault-tolerant integer division circuit is introduced in this chapter. In this design a restoring division algorithm as well as quantum restoring integer division circuitry are introduced.

DOI
10.1088/978-0-7503-5683-1ch19

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This part of the book describes some background and preliminary studies of quantum fault-tolerant circuits in this chapter. The approach for designing a fault tolerant quantum adder (full-adder) is given in this chapter. A design for a fault tolerant multiplier (signed multiplier) is also shown. Finally, the design procedure for a quantum fault-tolerant integer division circuit is introduced in this chapter. In this design a restoring division algorithm as well as quantum restoring integer division circuitry are introduced.
Quantum circuits for mathematical functions such as division are necessary to use quantum computers for scientific computing. Quantum circuits based on Clifford+T gates can easily be made fault-tolerant but the T gate is very costly to implement. The small number of qubits available in existing quantum computers adds another constraint on quantum circuits. As a result, reducing T-count and qubit cost have become important optimization goals. The design of quantum circuits for integer division has caught the attention of researchers and designs have been proposed in the literature. However, these designs suffer from excessive T gate and qubit costs. Many of these designs also produce significant garbage output resulting in additional qubit and T gate costs to eliminate these outputs. In this work, we propose two quantum integer division circuits. The first proposed quantum integer division circuit is based on the restoring division algorithm and the second proposed design implements the non-restoring division algorithm. Both proposed designs are optimized in terms of T-count, T-depth and qubits. Both proposed quantum circuit designs are based on (i) a quantum subtractor, (ii) a quantum adder-subtractor circuit, and (iii) a novel quantum conditional addition circuit. Our proposed restoring division circuit achieves average T-count savings from 79.03 to 91.69 percent compared to the existing works. Our proposed non-restoring division circuit achieves average T-count savings from 49.22 to 90.03 percent compared to the existing works. Further, both our proposed designs have linear T-depth. We also illustrate the application of the proposed quantum division circuits in quantum image processing with a case study of quantum bilinear interpolation.
The performance of existing technology for implementing digital circuits based on irreversible logic is closely reaching its limit. Conventional logic circuits result in heat dissipation whenever there is an information loss. Hence reversible logic is attaining major consideration in the perspective of evolving technologies such as quantum computing as there isno information loss and there is a unique mapping between the input vectors and output vectors. A reversible gate is supposed to be parity preserving if there existsimilarity between input parityand the outputparity.To construct reliable fault-tolerant reversible systems elements should be of fault-tolerant reversiblestructures.Adder circuits are studied extensively since their performance can directly affect the entire digital system. This paper presents a Toffoli gate (TG) based fulladderwhich serves as a fundamental component in constructing a ripple carry adder. Further a parity preserving Toffoligate based full adder is presented which was utilized to develop a fault-tolerant Ripple Carry Adder without compromising on its performance.The proposed designs have been simulated using IBM Quantum Simulator and have been verified for their correctness. The proposed adders will serve as vital design components in developing fault-tolerant reversible arithmetic and logic unit.
Reversible logic has drawn great attention in recent years due to its emerging propagation in diverse range of areas. In this paper, we present a novel approach to unite addition and subtraction operations; circuits that perform addition/subtraction operations using fault tolerant reversible gates with fault detection capability. Adder and subtractor are basic building blocks of any Arithmetic Logic Unit; in this manner we first present the concept of merging those two circuits into one logical block. Then we introduce all possible approaches to construct fault tolerant united addition-subtraction circuit for not only reducing the number of gate but also minimizing quantum cost and garbages of circuit at a meaningful level. We demonstrate three types of half-adder/subtractor circuits and four types of full-adder/subtractor circuits. Again, we depict an algorithm based on our novel concept and we also present simulations on our proposed circuits. Besides, the comparative analysis of our proposed compact method shows our proposed circuit outperform than existing circuit as highest improvements of proposed circuits are 33.33% for garbage output, 26.66% for quantum cost and 50% for gate count. Finally, overall significance of our proposed designs is presented in conclusion.
Arithmetic operations are an important component of many quantum algorithms. Optimizing quantum circuits for these operations therefore leads to more efficient implementations of the corresponding algorithms. In this paper, we develop new fault-tolerant quantum circuits for various integer division algorithms (both reversible and non-reversible). These circuits, when implemented in the Clifford+T gate set, achieve improvements in the asymptotic T-count and CNOT-count from O(n2)O(n^2)O(n2) to O(nm)O(nm)O(nm), and in the asymptotic T-depth from O(n2)O(n^2)O(n2) to O(nlog⁡m)O(n \log m)O(nlogm), where nnn and mmm are the bit lengths of the dividend and divisor, respectively. The qubit counts are significantly lower than those in previous works. We achieve this through careful modifications of the division algorithms and by expressing them in terms of a primitive we call COMP-N-SUB that compares two integers and conditionally subtracts them. We show that this primitive can be implemented at a cost, in terms of both Clifford and non-Clifford gates, comparable to that of one addition. By contrast, performing comparison and conditional subtraction separately would cost roughly as much as a controlled addition plus a regular addition.
Quantum computation has the potential to solve certain mathematical and physical problems faster than a classical computer. However, one of the key challenges to realizing a quantum computing device is controlling systematic errors and maintaining the coherence of the quantum state. In addition, once a scalable quantum computer is built, we must be able to fault-tolerantly communicate a quantum algorithm to the physical device. In this dissertation, we take several significant steps towards the realization of a quantum computer. We develop a framework for use with any proposed technology to map a quantum algorithm into fault-tolerant machine instructions. Within this framework, we combat errors and decoherence by introducing quantum error correction and fault tolerance into a quantum circuit. We analyze specific fault-tolerant circuitry on two general architectures, nonlocal and nearest-neighbor, to determine failure thresholds of the physical circuit components. These failure thresholds allow physicists to evaluate technology proposals. Our goal is to provide design tools, failure thresholds, and fault-tolerant constructions to combat the faultiness of quantum computation.