Towards Complete and Scalable Emulation of Quantum Algorithms on High-Performance Reconfigurable Computers
Esam El‐Araby, Naveed Mahmud, Mingyoung Jeng, Andrew MacGillivray, Manu Chaudhary, Alvir Nobel, Ishraq Islam, David Levy, Dylan Kneidel, Madeline R. Watson, Jack Bauer, Andrew Riachi
Contemporary quantum computers face many critical challenges that limit their usefulness for practical applications. A primary limiting factor is classical-to-quantum (C2Q) data encoding, which requires specific circuits for quantum state initialization. The required state initialization circuits are often complex and violate decoherence constraints, particularly for I/O intensive applications. Existing Noisy Intermediate-Scale Quantum (NISQ) devices are noise-sensitive and have low quantum bit (qubit) counts, thus limiting the applicability of C2Q circuits for encoding large and realistic datasets. This has made the study of complete and realistic circuits that include data encoding challenging and has also led to a heavy dependency on costly and resource-intensive simulations on classical platforms. In this work, we propose a cost-effective, classical-hardware-accelerated framework for realistic and complete emulation of quantum algorithms. The emulation framework incorporates components for the critical C2Q data encoding process, as well as architectures for quantum algorithms such as the quantum Haar transform (QHT). The framework is used to investigate optimizations for C2Q and QHT algorithms, and the corresponding optimized quantum circuits are presented. The framework is implemented on a High-Performance Reconfigurable Computer (HPRC) which emulates the proposed QHT circuits combined with proposed C2Q data encoding methods. For performance benchmarks, CPU-based emulations and simulations on a state-of-the-art quantum computing simulator are also carried out. Results show that the proposed hardware-accelerated emulation framework is more efficient in terms of speed and scalability compared to CPU-based emulation and simulation.
Contemporary quantum computers face many critical challenges that limit their usefulness for practical applications. A primary limiting factor is classical-to-quantum (C2Q) data encoding, which requires specific circuits for quantum state initialization. The required state initialization circuits are often complex and violate decoherence constraints, particularly for I/O intensive applications. Existing Noisy Intermediate-Scale Quantum (NISQ) devices are noise-sensitive and have low quantum bit (qubit) counts, thus limiting the applicability of C2Q circuits for encoding large and realistic datasets. This has made the study of complete and realistic circuits that include data encoding challenging and has also led to a heavy dependency on costly and resource-intensive simulations on classical platforms. In this work, we propose a cost-effective, classical-hardware-accelerated framework for realistic and complete emulation of quantum algorithms. The emulation framework incorporates components for the critical C2Q data encoding process, as well as architectures for quantum algorithms such as the quantum Haar transform (QHT). The framework is used to investigate optimizations for C2Q and QHT algorithms, and the corresponding optimized quantum circuits are presented. The framework is implemented on a High-Performance Reconfigurable Computer (HPRC) which emulates the proposed QHT circuits combined with proposed C2Q data encoding methods. For performance benchmarks, CPU-based emulations and simulations on a state-of-the-art quantum computing simulator are also carried out. Results show that the proposed hardware-accelerated emulation framework is more efficient in terms of speed and scalability compared to CPU-based emulation and simulation.
Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic) pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT) and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC) was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.
Noisy Intermediate-Scale Quantum (NISQ) devices face many critical challenges that limit their usefulness for practical applications. A primary challenge is classical-to-quantum (C2Q) data encoding, which requires specific circuits for quantum state initialization, particularly for I/O intensive applications. The required state initialization circuits are often complex, and violate decoherence constraints. Another critical challenge for quantum computers is quantum state readout or quantum-to-classical (Q2C) data decoding. The general approach for Q2C involves repeated sampling of the quantum circuit, which often incurs significant overhead in the overall execution time. In this paper, we propose time-efficient methods for C2Q data encoding and Q2C data decoding for quantum algorithms. Decoherence optimized circuits for C2Q data encoding are presented along with analysis of their circuit depths. For Q2C, a novel approach based on more efficient sampling of the output state using the Quantum Wavelet Transform is proposed. The proposed methods are experimentally evaluated on a state-of-the-art quantum computing device from IBM Quantum using realistic multi-spectral data. Experimental results are consistent with our theoretical expectations and confirm the efficiency of our proposed methods compared to existing techniques. More specifically, our proposed C2Q method demonstrates a theoretical 2x reduction in circuit depth which resulted in improving the experimental execution time compared to the state-of-the-art, while our Q2C method achieved a maximum of 89% reduction in circuit sampling time.
With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.
The general approach for emulating quantum algorithms on classical platforms has been through representing them as gate-based quantum circuits. However, direct implementation of quantum circuits significantly increases the hardware resource utilization and system latency of classical emulators. In this paper, we investigate multiple implementation models alternative to conventional emulation approaches, as feasible solutions to the scalability problem in classical emulation of quantum circuits. In the first model, the quantum circuit functionality is reduced to equivalent, arithmetic (multiply-and-accumulate) operations and combined with two computation methods, based on lookup and dynamic generation. In the second model, a kernel operation is extracted from the quantum circuit based on its functionality, and the kernel is iterated through all input quantum states. The proposed emulation models provide space and time optimizations, significantly reducing resource utilizations and latencies and improving scalability. We use these models to develop a highly scalable hardware emulator that is based on reconfigurable technology for efficient simulations of full quantum algorithms and circuits. Our hardware implementations support single precision floating point arithmetic for improved accuracy, and contain fully pipelined designs for high throughput. We investigate quantum algorithms such as quantum Fourier transform and quantum wavelet transform and explore different hardware architectures and optimizations. Experimental results and analysis are provided for the architectures in terms of resource consumption and emulation time. The experiments are carried out on a high-performance reconfigurable computing system and the obtained results show that the proposed emulator is feasible for running and testing a variety of quantum algorithms.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
ABSTRACT In recent years, quantum emulation has attracted increasing attention as a practical approach for developing and evaluating quantum algorithms. However, existing solutions often face challenges in achieving broad applicability, high performance, and efficient utilization of hardware resources and memory. To address these limitations, this paper presents the high‐performance quantum emulation accelerator (HPQEA), a hardware architecture based on the state‐vector emulation approach. The proposed design incorporates four key techniques: a strict data storage strategy, a superior flexible processing element network, an optimized and parallelized CX swapper, and a high‐bandwidth memory‐based bulk data transfer engine. Implementation and evaluation on the Alveo U280 FPGA platform demonstrate that HPQEA can emulate quantum circuits efficiently while maintaining high fidelity and low mean square error. Experimental results show that for QFT benchmarks, HPQEA achieves up to 21,093 faster execution than the NVIDIA A100 GPU for circuits with fewer than 20 qubits. Moreover, the comparison with FPGA‐based related works shows promising results with significant speedup in terms of normalize gate speed from 2.77 to 1448.37. In addition, the architecture demonstrates strong energy efficiency, reducing power consumption by up to 15.58 compared to the Intel i9‐10940X CPU and 80.83 compared to the GTX 1080 GPU. These results highlight the scalability, efficiency, and practicality of HPQEA as a hardware platform for accelerating quantum algorithm emulation.