Large error rates of quantum bits (qubits) are one of the main difficulties in the development of quantum computing. Performing quantum error correction (QEC) with surface codes is considered the most promising approach to reduce the error rates of qubits effectively. To perform error correction, we need an error-decoding unit, which estimates errors in the noisy physical qubits repetitively, to create a robust logical qubit. While complicated graph-matching problems must be solved within a strict time restriction for the error decoding, several hardware implementations that satisfy the restriction at a large code distance have been proposed.
Large error rates of quantum bits (qubits) are one of the main difficulties in the development of quantum computing. Performing quantum error correction (QEC) with surface codes is considered the most promising approach to reduce the error rates of qubits effectively. To perform error correction, we need an error-decoding unit, which estimates errors in the noisy physical qubits repetitively, to create a robust logical qubit. While complicated graph-matching problems must be solved within a strict time restriction for the error decoding, several hardware implementations that satisfy the restriction at a large code distance have been proposed.
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (440 ns) of current solid-state qubit technologies for both ASIC designs (<30 ns) and FPGA implementations (<90 ns). These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1× and 6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs average latency, and by 13% under a strict 1μs deadline.
Current quantum processors are fragile, noisy and fairly limited in both quantity and quality with tens of qubits and physical error rates of around 10^-3. To realize practical quantum applications, however, error rates need to be below 10^-15 across millions of qubits. To bridge this gap and fully harness the potential of quantum computers, quantum error correction (QEC) is essential. QEC codes are designed to protect quantum information by redundantly encoding it onto multiple physical qubits. This encoding allows for the detection and correction of local errors affecting individual qubits, e.g., through stabilizer measurements. Importantly, if the physical error rates are below a specific threshold, QEC codes can exponentially suppress logical error rates by increasing the number of physical qubits involved. This is essential for achieving fault-tolerant computations, which are key to unlocking the full potential of quantum computers. The work presented in this thesis focuses on the implementation and optimization of small-scale QEC experiments using the surface code and flux-tunable superconducting qubits (Transmons). It addresses several key challenges: enhancing two-qubit gate fidelity in Surface-4 (Chapter 2), implementing an error-detection code with Surface-7 (Chapter 3), automating the calibration and benchmarking of the building blocks in Surface-17 (Chapter 4), reducing leakage into higher excited states with leakage reduction units (Chapter 5), assessing and enhancing the performance of logical qubits (Chapters 7 and 8).
Quantum error correction (QEC) represents a critical enabler for fault-tolerant quantum computing, protecting fragile quantum states from decoherence and operational errors. This paper provides a comprehensive analysis of leading quantum error correction schemes, focusing on surface codes and topological codes within the context of Noisy Intermediate-Scale Quantum (NISQ) era processors. We examine the theoretical foundations of stabilizer codes, compare surface code implementations with code distances ranging from d=3 to d=17, and analyze topological codes including toric codes and color codes. Our investigation encompasses syndrome extraction circuits, logical qubit encoding strategies, and threshold analysis for contemporary quantum hardware platforms. Performance metrics reveal that surface codes achieve error thresholds of approximately 1% with realistic noise models, while topological codes offer architectural advantages for specific qubit connectivity constraints. We discuss implementation challenges on current NISQ processors including IBM Quantum, Google Sycamore, and IonQ systems, addressing qubit overhead, gate fidelity requirements, and decoding algorithms. This analysis provides insights for selecting appropriate error correction schemes based on application requirements and hardware capabilities.
Quantum Computing is a computing framework that takes advantage of unique quantum mechanical properties (such as superposition and entanglement) to perform calculations and implement algorithms that could offer exponential speed-ups over classical computing. However, in physical implementations of such quantum computers, qubits – the fundamental components of these systems – can accumulate errors that must be accounted for. In order to mitigate these errors, various quantum error correction (QEC) codes have been developed, including the repetition code and surface codes. In this experiment I implement and evaluate three types of QEC codes on the Qiskit simulator to compare their efficacy and applicability in correcting for different kinds of errors. I hypothesize that surface codes, with their more effective design and range of correction methods, should perform the best with much lower error thresholds and resultant logical error rates. The results support the hypothesis and suggest that surface codes are a viable method of implementing scalable error correction in quantum computers.
Quantum technologies have the potential to solve certain computationally hard problems with polynomial or super-polynomial speedups when compared to classical methods. Unfortunately, the unstable nature of quantum information makes it prone to errors. For this reason, quantum error correction is an invaluable tool to make quantum information reliable and enable the ultimate goal of fault-tolerant quantum computing. Surface codes currently stand as the most promising candidates to build near term error corrected qubits given their two-dimensional architecture, the requirement of only local operations, and high tolerance to quantum noise. Decoding algorithms are an integral component of any error correction scheme, as they are tasked with producing accurate estimates of the errors that affect quantum information, so that they can subsequently be corrected. A critical aspect of decoding algorithms is their speed, since the quantum state will suffer additional errors with the passage of time. This poses a connundrum, where decoding performance is improved at the expense of complexity and viceversa. In this review, a thorough discussion of state-of-the-art decoding algorithms for surface codes is provided. The target audience of this work are both readers with an introductory understanding of the field as well as those seeking to further their knowledge of the decoding paradigm of surface codes. We describe the core principles of these decoding methods as well as existing variants that show promise for improved results. In addition, both the decoding performance, in terms of error correction capability, and decoding complexity, are compared. A review of the existing software tools regarding surface codes decoding is also provided.