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CRC Press eBooks

Control Unit Micro-architecture

Nadia Nedjah, Luiza de Macedo Mourelle

Published Jan 5, 2023• 0 citations
Publisher

Abstract

This chapter describes the micro-architecture of this unit and define the main control components required to implement the execution of the quantum micro-instructions. It discusses the tensor product controller, which controls the three main operations: tensor product of quantum bits; matrix product of quantum bits; tensor product of operators. The control unit UCO synchronizes the operation of the co-processor’s remaining components mainly using a micro-program together with some auxiliary components. Based on the instructions prescribed by the main processor, unit UCO will orchestrate the other components of the macro-architecture as well as its internal components by means of planned micro-orders and some specific controllers. The MPR address register is implemented as an up-counter with a preset option. Component QbTPCtrl controls the read/write addresses for memory MQB, the control records of memory MQC as well as the multiplexers and registers of unit UCA so as it can produce the requested tensor product.

DOI
10.1201/9781003344094-8

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•Jan 1, 2019•1 citation
This chapter describes the micro-architecture of this unit and define the main control components required to implement the execution of the quantum micro-instructions. It discusses the tensor product controller, which controls the three main operations: tensor product of quantum bits; matrix product of quantum bits; tensor product of operators. The control unit UCO synchronizes the operation of the co-processor’s remaining components mainly using a micro-program together with some auxiliary components. Based on the instructions prescribed by the main processor, unit UCO will orchestrate the other components of the macro-architecture as well as its internal components by means of planned micro-orders and some specific controllers. The MPR address register is implemented as an up-counter with a preset option. Component QbTPCtrl controls the read/write addresses for memory MQB, the control records of memory MQC as well as the multiplexers and registers of unit UCA so as it can produce the requested tensor product.
This chapter provides an overall view regarding the function that must be executed by the calculation unit. The Calculation Unit UCA of the macro-architecture is responsible for multiplication of complex numbers, necessary for the execution of the tensor product of quantum operators, tensor product of q-bits, matrix product of operators and quantum register of q-bits as well as the sum of complex numbers. The construction of a quantum register starts by the tensor product of the q-bits specified in the first two instructions of the quantum operation. The q-bit that is specified in the third instruction would be tensorally multiplied with the register of two q-bits that was prepared in the previous iteration. The ability to simultaneously process more coefficients is possible, with the replication of the aforementioned sets, which must be accompanied by some minimal changes in the number of inputs corresponding to the multiplexers.
This conclusion presents some closing thoughts on the concepts covered in the preceding chapters of this book. The book discusses the basic elements of quantum computing are presented to help the reader in understanding the architecture and functionalities of the proposed co-processor design. Q-bit entanglement is a procedure used in quantum algorithms. The proposed macro-architecture presents a number of components that could possibly be kept in a co-processor version with greater processing capacity. The control unit is the component that manages all the remaining units present in the co-processor’s data path, using control memory and auxiliary components. The control path automates some elementary tasks and contributes to simplify the microprogram. The pipeline organization of the architecture to streamline the quantum operation through the use of auxiliary complex number multipliers for the performance of the matrix product of the already calculated lines regarding the new operator under construction would reduce the wait time for the usage of all the required calculations.
This chapter discusses the overall hardware architecture of a quantum processor. Emulation of quantum processing requires primarily an efficient way to store and retrieve quantum information. The quantum processor employs different purpose memories. The proposed co-processor implements a quantum machine capable of performing certain quantum operations on a set of q-bits that form the machine quantum state. It is an isolated system that interacts with a host processor through communication channels. The main processor sends properly formatted commands that invoke quantum operations on q-bits, to manipulate the quantum state. The channel configuration is used because it considers the sequential characteristic of a quantum algorithm due to the potential dependence of the result of the previous operation on one or more q-bits. The full-duplex configuration would also be possible, given the required control related to data dependency. The interaction between the units and memories that compose the co-processor is done via data buses, address buses and/or control buses.
This chapter discusses the execution of a quantum operation that manipulates a single quantum bit, showing the time diagram during its simulation. It illustrates the execution of an operation on non-entangled quantum bits, showing the time diagram during its simulation. When performing a quantum operation on two or more q-bits where at least one of them is entangled with another and/or when the quantum operation causes entanglement, the construction of the quantum operator by means of a tensor product is required. The coefficients of the basic quantum operators are read from memory MOP and stored in memory MSC when the operator is constructed for two q-bits. The construction of an operator for three or more q-bits requires the reading and writing of the coefficients in MSC, eventually occurring simultaneously, but always at different addresses.
This chapter discusses the main operation of tensor product, which is behind almost all quantum information manipulation. Tensor products are exploited in a similar manner to yield quantum operators to be used with quantum states of two or more quantum bits. The magnitude of the inversion depends on the state of the control q-bit. It can be said that the CNOT operator is a NOT operator dependent on a second q-bit. It can be constructed out of two chained H operators. The Toffoli operator can be seen as an extension of the CNOT port. It is considered universal and it is possible to build based on any other quantum operator. The chapter shows that if not handled efficiently, it would require a lot of memory space, which makes the design emulate a quantum processor quite expensive to produce.
Quantum Computing is an emerging field of technology with the promise that engineered quantum systems can address hard problems such as, problems with exponential compute complexity in Chemistry, Genomics, Optimization and many more applications. Quantum Computer Architecture is an area of research targeted for the NISQ-era quantum computing and little research has been done for development of a scalable classical control and read-out infrastructure for the quantum processors. The project is aimed at study of SoC-FPGA design methodology and architecture design for control of quantum processor. The targeted quantum hardware is the Spin-Qubit in Semiconductor Quantum Dot Chip. The project is intended for understanding the design and working of a silicon-spin qubit for a computer (architecture) engineer. It further helps identify necessities for an architecture, Instruction Set requirements, bottlenecks and future challenges (specific to Spin-Qubit quantum processor) that would help in better designs for new control architectures. The objective of this thesis is directed towards addressing the architectural challenges for the quantum-classical hardware for controlling the NISQ-era quantum devices and beyond. We analyze the control infrastructure requirements and propose a micro-architecture and waveform generation methodology to integrate the physical device with the quantum compilation tool-chain.