IEEE International Conference on Quantum Computing and Engineering (QCE)
Latest developments in the Sinara open hardware ecosystem
Paweł Kulik, Mikołaj Sowiński, Grzegorz H. Kasprowicz, D. T. C. Allcock, Christopher J. Ballance, Sébastien Bourdeauducq, J. Britton, Michał Gąska, T. P. Harty, Jakub Jarosiński, Robert Jördens, Marcin Kiepiela, Norman Krackow, D. P. Nadlinger, Krzysztof T. Pozniak, Tomasz Przywózki, D. H. Slichter, Filip Świtakowski, Marius Weber, Andrzej Wojciechowski, Weida Zhang
The complexity of quantum experimentation setups generates demand for a hardware platform that ensures means of standardization of the equipment used as well as setup repeatability.Sinara Hardware is an open-source answer to those challenges. It offers a modular architecture and well over 50 different modules. While originating from ion trapping experiments, it provides an ecosystem that can meet a wide range of quantum experimentation needs. Accompanied by researchers and engineers from different universities and private companies, Sinara Hardware is not only a hardware platform but also a vibrant community.Sinara Hardware is developed along with an open-source control system - ARTIQ. ARTIQ provides a high-level programming interface along with experiment management tools. It offers nanosecond timing accuracy, sub-microsecond latency and means of timing distribution across several controller modules.This poster covers the developments from the last 2 years in the Sinara Hardware project. The most interesting novelties are: CERN Distributed IO Tier (DIOT) integration that will introduce backplane for communication and will enable use of DIOT Zynq UltraScale+ based controller; Artix-7 based FMC (FPGA Mezzanine Card) carrier along with two Sinara-dedicated FMCs: Shuttler - 125 MSPS 16 ch. 16-bit DAC (Digital to Analog Converter), with separate analog front end for application versatility and Waver - 1.5 GSPS 4 ch. 16-bit DAC; Unified Arbitrary Waveform Generator Framework as a common firmware platform for Sinara DAC applications as well as Xilinx RFSoC-based high bandwidth signal generator. Additionally, an overview of what is to be expected in future developments is shown.
The complexity of quantum experimentation setups generates demand for a hardware platform that ensures means of standardization of the equipment used as well as setup repeatability.Sinara Hardware is an open-source answer to those challenges. It offers a modular architecture and well over 50 different modules. While originating from ion trapping experiments, it provides an ecosystem that can meet a wide range of quantum experimentation needs. Accompanied by researchers and engineers from different universities and private companies, Sinara Hardware is not only a hardware platform but also a vibrant community.Sinara Hardware is developed along with an open-source control system - ARTIQ. ARTIQ provides a high-level programming interface along with experiment management tools. It offers nanosecond timing accuracy, sub-microsecond latency and means of timing distribution across several controller modules.This poster covers the developments from the last 2 years in the Sinara Hardware project. The most interesting novelties are: CERN Distributed IO Tier (DIOT) integration that will introduce backplane for communication and will enable use of DIOT Zynq UltraScale+ based controller; Artix-7 based FMC (FPGA Mezzanine Card) carrier along with two Sinara-dedicated FMCs: Shuttler - 125 MSPS 16 ch. 16-bit DAC (Digital to Analog Converter), with separate analog front end for application versatility and Waver - 1.5 GSPS 4 ch. 16-bit DAC; Unified Arbitrary Waveform Generator Framework as a common firmware platform for Sinara DAC applications as well as Xilinx RFSoC-based high bandwidth signal generator. Additionally, an overview of what is to be expected in future developments is shown.
Sinara, an open-source hardware ecosystem, has been designed to facilitate quantum experiments' efficient man-agement. Abiding by the CERN Open Hardware License, Sinara comprises over 50 modules, most of which are commercially available, representing a broad spectrum of capabilities. A crucial element of Sinara is its integration with the Advanced Real-Time Infrastructure for Quantum physics (ARTIQ) control system. This combination provides researchers with a robust toolkit with capabilities such as 1 ns timing resolution. It also includes a comprehensive suite of tools designed to manage experiment scheduling, versioning, results storage, and hardware management, enhancing the efficiency of quantum experiment workflows. The poster presents proposed development of Sinara based control system for a commercially available ion trap solution, with a systematic strategy to replace components of the control system with Sinara modules. This method affords valuable hands-on experience that will help in the design of future modules and the enhancement of existing ones. Proposed Sinara control system is to be made up of several subsystems, including high voltage controls, electrical controls, shuttling and readout, and laser controls. Each subsystem is managed through a PC and operated via ARTIQ or MQTT protocol, providing a structured framework for management. The subsystems utilize several advanced hardware components, including the Kasli v2 controller, Shuttler DAC, and DIOT STM Controller, among others.
Trapping ions, performing qubit operations and quantum multi-qubit gates require complex pulse spectra on several frequency bands. The Smart Arbitrary Waveform Generators (SAWG) Sayma and Phaser are designed to trap control and generate the Short-time Fourier transform (STFT) pulses. They have quad channels of over 1.2 GS/s (Giga Samples per second) 16-bit DACs and a few MS/s (Mega Samples per second) ADCs. These modules are dedicated to implementing qubit operations, both optically and electronically. The Sayma and Phaser modules are part of the Sinara family - a modular, open-source measurement and control hardware ecosystem dedicated to quantum applications that require deterministic high-resolution timing. The hardware is controlled and managed by the ARTIQ open-source software platform, which provides nanosecond timing resolution and sub-microsecond latency via a high-level programming language. We present the Sayma and the Phaser construction and obtained characteristics.
The Sinara hardware platform is a modular, opensource measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and submicrosecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics.
Ion trap quantum computers are complex optoelectronic systems that require several electronic subsystems orchestrated to sub-1ns precision, both low-noise and high speed. WUT developed a modular control system in EEM/DIOT form factor called SINARA (Standardised Instrumentation Architecture for Research Applications) [1]. SINARA became the de facto standard in atomic and Molecular laboratories worldwide; a few leading quantum computer manufacturers also use it. Its success, which can be attributed to the open-source, open-hardware licensing model, has significantly advanced the field of quantum computing by providing a reliable and adaptable control system. SINARA was primarily developed for lab applications but recently has been transformed into an industrial form factor (DIOT [5]) because many lab projects have turned into spin-offs and startups.The scaling of quantum computers creates several technological issues. Most topologies are enclosed in a vacuum and use cryogenic temperatures. Future quantum computer architectures need to implement electronic control systems capable of steering hundreds of thousands of electrodes with high precision and relatively high voltage of a few dozen V. Within the framework of the Quantera SIQCI [3] project, a collaborative effort aimed at advancing the field of quantum computing, we are building a demonstrator of such a scalable control system. An essential step of the design process is characterising a standard 180nm high voltage process at temperatures below 10 K. The next step is updating the process PDK and designing the test structures using updated models. This paper presents the requirements for such a control system, the first results of the measurements and the design methodology.Furthermore, this talk will unveil the first coherent operations results performed on ions trapped in the WUT labs using the SINARA system, marking a significant milestone in our system’s practical applications.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration.
To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits.
Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.