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IEEE International Symposium on Circuits and Systems proceedings

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device

Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, Koji Inoue

Published May 28, 2022• 2 citations
Publisher

Abstract

This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.

DOI
10.1109/iscas48785.2022.9937317

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This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.
CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.
A single-flux-quantum (SFQ) arithmetic logic unit (ALU) was designed and tested to evaluate the effectiveness of introducing dynamically reconfigurable logic gates in the design of a superconducting logic circuit. We designed and tested a bit-serial SFQ ALU that can perform six arithmetic/logic functions by using a dynamically reconfigurable AND/OR gate. To ensure stable operation of the ALU, we improved the operating margin of the SFQ AND/OR gate by employing a partially shielded structure where the circuit is partially surrounded by under- and over-ground layers to reduce parasitic inductances. Owing to the introduction of the partially shielded structure, the operating margin of the dynamically reconfigurable AND/OR gate can be improved without increasing the circuit area. This ALU can be designed with a smaller circuit area compared with the conventional ALU by using the dynamically reconfigurable AND/OR gate. We implemented the SFQ ALU using the AIST 2.5kA/cm2 Nb standard process 2. We confirmed high-speed operation and correct reconfiguration of the SFQ ALU by a high-speed test. The measured maximum operation frequency was 30GHz.
Abstract Single-flux-quantum (SFQ) circuits are promising candidates for post-Moore integrated circuits owing to their ultra-high-speed operation and low power consumption. However, limitations in current superconducting fabrication processes pose significant challenges to achieving area-efficient SFQ-based microprocessors, particularly in the design of compact arithmetic logic units (ALUs). Unary computing enables arithmetic operations using extremely simple logic, but typically suffers from long computation latency. This paper focuses on unary computing for superconducting circuits that exploits the complementary characteristics of SFQ logic and unary computing. The ultra-high-speed nature of SFQ circuits compensates for the inherent latency of unary computation, while unary computing enables an ultra-low hardware cost by substantially reducing circuit complexity. Based on this concept, we introduce a unary computing methodology tailored for SFQ circuits and design a superconducting unary ALU with ultra-low hardware cost. The proposed ALU requires only 183 Josephson junctions (JJs), achieving approximately 88.2% reduction in JJ count and 80.4% reduction in area compared with a conventional bit-serial SFQ ALU. The proposed design, including binary-to-unary and unary-to-binary converters, was fabricated using a 10 kA cm −2 Nb four-layer superconducting circuit fabrication process and experimentally verified to operate correctly at approximately 72 GHz. The total power consumption at this frequency is approximately 58.9 µ W. This work quantitatively demonstrates the effectiveness of combining unary computing with SFQ circuits for ultra-low-cost processing systems and provides superconducting circuits as a new design option for alternative computation paradigms, such as unary computing.
We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1 bit arithmetic logic unit (ALU) block. The circuit consists of three DC current driven SFQ switches and a half-adder. We successfully tested the half-adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half-adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached two switches at the input ports of the half-adder to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this set-up, the circuit was successfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES 1 kA cm −2 Nb Josephson junction fabrication process.
We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.
Single flux quantum (SFQ) logic circuits, in which a single flux quantum is used for an information carrier, have a possibility to open a new digital system operated with over 100 GHz clock frequencies at extremely low power dissipations. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits with high speeds has been done. By taking advancements in these designing tools, circuits including more than several thousands junctions easily operated with the clock frequency of more than several tens GHz. Applications of SFQ circuits such as high performance computers, high end router and high end servers are being developed in the world taking advantages of the high through-put nature and the low power dissipation of the SFQ logic.