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Modern Physics Letters A

The implementation of the enhanced quantum floating-point adder

Shantao Zhao, Hai-Sheng Li, Guiqiong Li, Xiaohu Tang

Published Aug 30, 2022• 3 citations
Publisher

Abstract

The quantum adder is a vital arithmetic operation for quantum algorithms. However, the existing quantum floating-point adders only considered the case of two normal numbers. In this paper, we propose an enhanced quantum floating-point adder based on IEEE 754 standard. First, we divide quantum floating-point adders into four cases: the normal case, subnormal case, mixed case, and special case. Then, we propose a result-sign and mantissa-sign determining unit to avoid conversion from sign-magnitude to two complements. Moreover, we design a new quantum leading zero detector with the optimized T-depth and T-count. Comparison results reveal that the proposed floating-point adder has lower circuit width, T-depth, and T-count than the current works.

DOI
10.1142/s0217732322501693

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The quantum adder is a vital arithmetic operation for quantum algorithms. However, the existing quantum floating-point adders only considered the case of two normal numbers. In this paper, we propose an enhanced quantum floating-point adder based on IEEE 754 standard. First, we divide quantum floating-point adders into four cases: the normal case, subnormal case, mixed case, and special case. Then, we propose a result-sign and mantissa-sign determining unit to avoid conversion from sign-magnitude to two complements. Moreover, we design a new quantum leading zero detector with the optimized T-depth and T-count. Comparison results reveal that the proposed floating-point adder has lower circuit width, T-depth, and T-count than the current works.
The implementation of quantum computing processors for scientific applications includes quantum floating points circuits for arithmetic operations. This work adopts the standard division algorithms for floating-point numbers with restoring, non-restoring, and Goldschmidt division algorithms for single-precision inputs. The design proposals are carried out while using the quantum Clifford+T gates set, and resource estimates in terms of numbers of qubits, T-count, and T-depth are provided for the proposed circuits. By improving the leading zero detector (LZD) unit structure, the proposed division circuits show a significant reduction in the T-count when compared to the existing works on floating-point division.
Implementation of floating-point arithmetic with consistent rounding is a critical component of many quantum algorithms. Quantum circuit implementations for squaring and division serve as examples here. This work was motivated by ongoing work in developing quantum algorithms for scientific and engineering computing applications, where this type of arithmetic often forms part of the algorithm. A key feature of the work is the use of a reduced-precision floating-point representation of real data specifically designed for near-term future quantum computing hardware with a limited number of qubits (e.g., less than 100) and with an increased level of fault tolerance as compared to current quantum computing hardware. The quantum circuit implementations of the squaring of a floating-point number and the division of two floating-point numbers are detailed here, highlighting similarities in the quantum circuit implementation for the logical steps required for rounding-to-nearest in line with the IEEE 754 standard for the two arithmetic operations. This similarity is an important feature regarding future work where an automated generation of this type of quantum circuit from a set of standard modules and circuit templates is employed.
We propose a novel floating-point encoding scheme that builds on prior work involving fixed-point encodings. We encode floating-point numbers using Two's Complement fixed-point mantissas and Two's Complement integral exponents. We used our proposed approach to develop quantum algorithms for fundamental arithmetic operations, such as bit-shifting, reciprocation, multiplication, and addition. We prototyped and investigated the performance of the floating-point encoding scheme on quantum computer simulations by performing reciprocation on randomly drawn inputs and by solving first-order ordinary differential equations, while varying the number of qubits in the encoding. We observed rapid convergence to the exact solutions as we increased the number of qubits and a significant reduction in the number of ancilla qubits required for reciprocation when compared with similar approaches.
Abstract The development of quantum algorithms is facilitated by quantum circuit designs. A floating-point number can represent a wide range of values and is extremely useful in digital signal processing. A quantum circuit model to implement the floating-point division problem using the Newton-Raphson division algorithm is proposed in this paper. The proposed division circuit offers a significant savings in T-gates and qubits used in the circuit design when correlated with the state of art works proposed on fast division algorithms. The qubits savings are estimated around 17% and 20%, T-count savings are around 59.03% and 20.31%. Similarly, T-depth savings is estimated around 77.45% and 24.33% over the existing works.
There are several possible ways to encode random variables in a quantum state. The basis encoding of bit strings has paramount importance because it allows to load the values of a random variable through the superposition of corresponding basis states, and to then exploit quantum parallelism in processing algorithms. The basis encoding offers a natural way to represent an unsigned integer random variable, and extends to signed integers, as well as to fixed-point and floating-point variables. Each quantum representation of fractional numbers, however, involves a trade-off between accuracy and depth of manipulation circuits. Here, an efficient hybrid quantum-classical representation of quantum floating points is introduced. It combines a quantum register containing the values, with a classical register storing global information about the variable, namely the range and approximation tolerances. The sum and product operations are defined, in such a way as to ensure they are performed without overflow. By taking advantage of the stored classical information, the precision degradation that occurs due to rounding after repeated data manipulations, can be significantly reduced compared to known strategies. Ad hoc examples show up to around 90%90\%90% reduction in approximation, compared to previous techniques, after repeated additions. The method finds application in many algorithms of practical relevance and constitutes a significant advance in the design of arithmetic circuits with low depth and high accuracy.