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Indonesian Journal of Electrical Engineering and Computer Science

Single parity check node adapted to polar codes with dynamic frozen bit equivalent to binary linear block codes

Driss Khebbou, Idriss Chana, Hussain Ben-Azza

Published Nov 18, 2022• 4 citations
Publisher

Abstract

In the context of decoding binary linear block codes by polar code decoding techniques, we propose in this paper a new optimization of the serial nature of decoding the polar codes equivalent to binary linear block codes. In addition to the special nodes proposed by the simplified successive-cancellation list technique, we propose a new special node allowing to estimate in parallel the bits of its sub-code. The simulation is done in an additive white gaussian noise channel (AWGN) channel for several linear block codes, namely bose–chaudhuri–hocquenghem codes (BCH) codes, quadratic-residue (QR) codes, and linear block codes recently designed in the literature. The performance of the proposed technique offers the same performance in terms of frame error rate (FER) as the ordered statistics decoding (OSD) algorithm, which achieves that of maximum likelihood decoder (MLD), but with high memory requirements and computational complexity.

DOI
10.11591/ijeecs.v29.i2.pp816-824

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In the context of decoding binary linear block codes by polar code decoding techniques, we propose in this paper a new optimization of the serial nature of decoding the polar codes equivalent to binary linear block codes. In addition to the special nodes proposed by the simplified successive-cancellation list technique, we propose a new special node allowing to estimate in parallel the bits of its sub-code. The simulation is done in an additive white gaussian noise channel (AWGN) channel for several linear block codes, namely bose–chaudhuri–hocquenghem codes (BCH) codes, quadratic-residue (QR) codes, and linear block codes recently designed in the literature. The performance of the proposed technique offers the same performance in terms of frame error rate (FER) as the ordered statistics decoding (OSD) algorithm, which achieves that of maximum likelihood decoder (MLD), but with high memory requirements and computational complexity.
This paper aims to take advantage of the performances of polar decoding techniques for the benefit of binary linear block codes (BLBCs) with the main objective is to study the performances of the SSCL decoding for short-length BLBCs. Polar codes are one of the most recent error-correcting codes to be invented, and they have been mathematically demonstrated to be able to correct all errors under a specific situation, using the successive-cancellation decoder. However, their performances for real-time wireless communications at short block lengths remain less attractive. To take advantage of the performance of these codes in favor of error correction codes of short block length, an adaptation of the simplified successive-cancellation list as a decoder for polar codes for the benefit of short block length binary linear block codes is presented in this paper. This adaptation makes it possible to take advantage of the performances of less complex decoding methods for polar codes for BLBCs with latency and complexity optimization of the standard successive-cancellation list decoder. The experiment shows that the method can achieve the performances of the most famous order statistic decoder for binary linear block codes, which can achieve the performances of maximum-likelihood decoding with computational complexity and memory constraints.
Due to the ability to provide superior error-correction performance, the successive cancellation list (SCL) algorithm is widely regarded as one of the most promising decoding algorithms for polar codes with short-to-moderate code lengths. However, the application of SCL decoding in low-latency communication scenarios is limited due to its sequential nature. To reduce the decoding latency, developing tailored fast and efficient list decoding algorithms of specific polar constituent codes (special nodes) is a promising solution. Recently, fast list decoding algorithms are proposed by considering special nodes with low code rates. Aiming to further speedup the SCL decoding, this paper presents fast list decoding algorithms for two types of high-rate special nodes, namely single-parity-check (SPC) nodes and sequence rate one or single-parity-check (SR1/SPC) nodes. In particular, we develop two classes of fast list decoding algorithms for these nodes, where the first class uses a sequential decoding procedure to yield decoding latency that is linear with the list size, and the second further parallelizes the decoding process by pre-determining the redundant candidate paths offline. Simulation results show that the proposed list decoding algorithms are able to achieve up to 70.7% lower decoding latency than state-of-the-art fast SCL decoders, while exhibiting the same error-correction performance.
A parameterized universal decoding framework based on polar transformations was recently proposed to enable polar-style decoding of general binary linear block codes (BLBCs). However, existing parallelization methods for polar codes cannot be directly applied to this framework. The key obstacle is that these methods rely on static frozen-set structures, which are incompatible with the dynamic frozen constraints induced by polar transformations. To address this challenge, we revisit code automorphisms from a new perspective: instead of applying them to the codeword space, we let them act on the transformation parameter itself. We show that the BLBC automorphism group induces equivalence polar transformation classes. Crucially, all transformations within an equivalence class share the same polar subcode structure, eliminating the need for separate decoder designs. This insight enables a novel parallel decoding framework termed polar ensemble decoding (PED). By decoding multiple equivalent transformations simultaneously, PED exploits transformation diversity while maintaining decoder compatibility. Simulation results on extended BCH and extended Golay codes demonstrate that PED achieves near maximum-likelihood performance while significantly reducing the decoding latency compared to successive cancellation list (SCL) decoding.
Due to the unsatisfactory block error rate (BLER) performance of short or moderate block , the further development of polar codes is limited. In this paper, the parity-check codes concatenated cyclic redundancy check aided successive cancellation list (CA-SCL) decoding algorithms are studied. Then, an efficient concatenated method, double-parity-check CA-SCL (DP-CA-SCL) polar codes, is proposed according to exiting parity-check decoding algorithms. Not only can this new method improve the BLER performance in short or moderate block, but also it can guarantee the reduction of complexity relative to original CA-SCL method. The simulations in additive white Gaussian noise channel with binary phase shift keying modulation reveal that the DP-CA-SCL polar codes can provide significant performance gains. Comparing to the original CA-SCL decoding, there are 0.5 dB performance gains using proposed method at BLER of 10-3with (128, 64) polar codes. For another moderate block (256, 128) polar codes, it can also guarantee performance gains at least 0.18 dB.
A new decoding scheme aided by simulated annealing algorithm is proposed to further improve the decoding performance of successive cancellation (SC) for polar codes at the short block. We use simulated annealing to revise the decoding result of SC which cannot pass the CRC check. To generate the new neighbors, the decoder flips one bit from the set of the least unreliable information bits each time in the estimated source vector of SC decoding. Euclidean distance is used to measure the gap between the new neighbor solution and the received word so that the decoder can obtain a global optimal solution. Simulation shows that the proposed decoder has a performance gain about 0.5 dB in terms of frame error rate (FER) under short blocks in the additive white Gaussian noise (AWGN) channel compared to other basic decoders, while keeping a low time cost through a parameter tuning process.
Successive-Cancellation List (SCL) decoding of Polar codes, supported by a Cyclic Redundancy Check, achieves a distinguished error-correction performance at the cost of a high decoding complexity. The parallel decoding of constituent Single Parity Check (SPC) nodes of a Polar factor tree relevantly contributes to the implementation costs of high-throughput, deeply pipelined SCL decoding architectures. In this paper, we present algorithms to reduce the number of considered candidates in SPC nodes. For this purpose, we adapt the partial order-based Rate-1 node candidate generation algorithm to the constraints in SPC nodes and deduce a low-complexity algorithm suitable for efficient hardware implementation. Simulation results show that the presented algorithms preserve the error-correction performance with reduced hardware implementation costs. Additionally, an extended threshold in the candidate selection enables a trade-off between error-correction and implementation costs by a further reduction of the considered candidates. Furthermore, Application-Specific Integrated Circuit (ASIC) implementations of the optimized node and three decoders with a code length of 128 in a 28 nm technology are presented. Regarding area efficiency and energy efficiency, improvements of up to 350.8 % and 84.7 % are achieved for the single SPC node with its sorter, while the presented SCL decoder implementations with list size 8 outperform a state-of-the-art reference decoder by up to 32.4 % and 32.0 %, respectively.