Superconducting (SC) devices and circuits have been garnering immense interest in recent years. due to the emergence of several major applications that demand and justify cryogenic (cryo) cooling below 4 Kelvin temperature. Superconducting single flux quantum (SFQ) technology supports ultra-fast (hundreds of GHz) classical computing operations, far beyond the capabilities of the CMOS processors [1]. The energy demand of a recent prototype of a SC processor proved to be ~80X less than that of its semiconductor counterpart (considering cooling cost) [2]. SC devices/circuits have been used in several spacecrafts in the last few years [3]. The need to explore design prospects for SC devices/circuits has become more imperative. A Superconducting nanowire (ScNW) [4], [5] is among the most promising SC devices with possible applications in several avenues of cryogenic electronics. Recent demonstrations proved that the ScNWs can be utilized to design cryogenic oscillators [6], with possible usage in cryo-neuromorphic systems [7]. The dynamics of the ScNW oscillator is unlike any other non-SC oscillator. Hence, a systematic design space expiration is crucial to facilitate the adoption and incorporation of these unique oscillators in different avenues of cryo-electronics. In this work, we conduct a simulation-based study of the ScNW oscillators to identify the material/device-circuit co-design opportunities.
Superconducting (SC) devices and circuits have been garnering immense interest in recent years. due to the emergence of several major applications that demand and justify cryogenic (cryo) cooling below 4 Kelvin temperature. Superconducting single flux quantum (SFQ) technology supports ultra-fast (hundreds of GHz) classical computing operations, far beyond the capabilities of the CMOS processors [1]. The energy demand of a recent prototype of a SC processor proved to be ~80X less than that of its semiconductor counterpart (considering cooling cost) [2]. SC devices/circuits have been used in several spacecrafts in the last few years [3]. The need to explore design prospects for SC devices/circuits has become more imperative. A Superconducting nanowire (ScNW) [4], [5] is among the most promising SC devices with possible applications in several avenues of cryogenic electronics. Recent demonstrations proved that the ScNWs can be utilized to design cryogenic oscillators [6], with possible usage in cryo-neuromorphic systems [7]. The dynamics of the ScNW oscillator is unlike any other non-SC oscillator. Hence, a systematic design space expiration is crucial to facilitate the adoption and incorporation of these unique oscillators in different avenues of cryo-electronics. In this work, we conduct a simulation-based study of the ScNW oscillators to identify the material/device-circuit co-design opportunities.
Oscillators designed to function at cryogenic temperatures play a critical role in superconducting electronics and quantum computing by providing stable, low-noise signals with minimal energy loss. Here, we present a comprehensive numerical study of injection locking and mutual coupling dynamics in superconducting nanowire (ScNW)-based cryogenic oscillators. Using the design space of a standalone ScNW-based oscillator, we investigate two critical mechanisms that govern frequency synchronization and signal coordination in cryogenic computing architectures: (1) injection locking induced by an external AC signal with a frequency near the oscillator's natural frequency, and (2) the mutual coupling dynamics between two ScNW oscillators under varying coupling strengths. We identify key design parameters—such as shunt resistance, nanowire inductance, and coupling strength—that govern the locking range. Additionally, we examine how the amplitude of the injected signal affects the amplitude of the locked oscillation, offering valuable insights for power-aware oscillator synchronization. Furthermore, we analyze mutual synchronization between coupled ScNW oscillators using capacitive and resistive coupling elements. Our results reveal that the phase difference between oscillators can be controlled by tuning the coupling strength, enabling programmable phase-encoded information processing. These findings could enable building ScNW-based oscillatory neural networks, synchronized cryogenic logic blocks, and on-chip cryogenic resonator arrays.
Superconducting (SC) electronics (SCE) is one of the major requirements to develop a large-scale practical quantum computing system. (Figs. 1(a)) [1]. Currently, a room temperature conventional computer is used as the control processor which requires a huge number of lossy interconnects to connect with the qubits placed at a few millikelvin temperatures. This, in turn, limits the scalability of the quantum computing system up to hundreds of qubits which is not enough to achieve the full potential [2]. Therefore, along with a suitable cryogenic memory, a cryogenic (preferably superconducting) control processor is required to develop a quantum computing system with thousands of qubits. Moreover, SCE offers ultra-fast (hundreds of gigahertz) and highly energy efficient (sub attojoule/bit) performance [3]. Therefore, SCE is projected to achieve the department of energy (DOE) exascale goal which the conventional supercomputers failed to achieve (Fig. 1(b)) [4]. However, Josephson junction-based SC circuits suffer from limited integration density due to flux trapping, difficulty in driving large impedances, fanning out digital signals, and operating in noisy environments [5]. To address these existing issues, here, we present a novel reconfigurable SC logic circuit using a nano-cryotron (nTron) that can perform 1-input copy, 2-input AND and OR, and 3-input majority logic functionalities. This work can enable the implementation of highly scalable and energy-efficient SC processor since the use of only one device. To achieve the reconfigurable nature of the logic circuit, we utilize the multi-gate switching of nTron.
Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.
Cryogenic (cryo) memory devices, designed to operate at/below 4 Kelvin (K) temperature, is a prime enabler of practical quantum computing systems, and superconducting (SC) electronic platforms (Figs. 1(a), (b)) [1]. The state-of-the-art quantum algorithms require many arbitrary rotations which demand a large memory to store program instructions [2]. SC qubits (used in most of the existing quantum computing systems) are highly sensitive to noise and hence, to protect the qubit states from thermal disturbances, they are placed at a few milli-Kelvin (mK) temperature. Furthermore, to preserve the integrity of the quantum states, the SC qubits undergo continuous error correction schemes, requiring extensive memory and bandwidth [2]. Superconducting electronics (SCE) (targeted towards space applications, and high-performance computing) outperforms the conventional CMOS counterparts in terms of speed and energy-efficiency (Fig. 1(c)) [3]. Decades of research efforts have given rise to three major categories (and several sub-variants) of cryo-memories based on SC, non-SC, and hybrid technologies (Fig. 2) [2], [4]–[6]. However, the existing variants suffer from one or more of the following challenges - (i) limited scalability, (ii) process complexity, (iii) bulky peripherals, (iv) array-level interference, (v) volatility, and (vi) speed incompatibility. Therefore, a scalable cryo-memory system remains elusive. To address these existing issues, here, we present a novel cryo-memory system utilizing -(i) the polarization-induced Cooper-pair [7] modulation in a ferroelectric(FE)superconducting quantum interference device (SQUID) (Fig. 3(a)) [8], and (ii) current controlledSC↔non−SCswitching in a heater cryotron(hTron)(Fig. 4) [4]. Discrete prototypes of these devices have been demonstrated recently, but their coupled interactions (which we harness in our work) were never explored before.
Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.
Superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising technology for cryogenic applications (e.g., quantum computing, astronomy, metrology) thanks to its ultra-fast and low-energy characteristics. Therefore, recent efforts in SFQ-based computing have focused on developing fast and low-power SFQ processors for cryogenic applications. However, there still has been little progress toward a convincing SFQ processor design due to the critical performance challenges originating from its extremely deep pipeline. In this paper, we propose a super-fast and low-power in-order SFQ processor by tackling the challenges from the deep pipeline. First, we develop a minimal-depth SFQ processor pipeline with novel architecture-level ideas. Next, we conduct in-depth performance analyses and identify three real performance bottlenecks in the deeply pipelined SFQ processors (i.e., stall/flush logic, RAW stall, fetch unit). Finally, we propose SuperCore, our super-fast SFQ-based processor architecture, with three SFQ-friendly solutions that effectively resolve the identified bottlenecks. With our solutions applied, SuperCore achieves 11 times speed-up over the SFQ processor baseline. In addition, SuperCore achieves six times speed-up and consumes up to 193 times less power compared to in-order CMOS processors running at 4K.