Quantum Hardware for All.

Siyuan Niu, Adrien Suau, Gabriel Staffelbach +1 more

Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.

Susan Clark

Madhusudan Singh Irish Singh, Bharat S. Rawal

Archisman Ghosh, Debarshi Kundu, Avimita Chatterjee +1 more

Quantum Generative Adversarial Networks (qGANs) are leading image-generating quantum machine learning models. With the increasing demand for Noisy Intermediate-Scale Quantum (NISQ) devices, more third-party vendors are expected to offer quantum hardware as a service, raising the risk of proprietary information theft. To mitigate this, we propose a novel watermarking technique that uses the noise signature embedded during qGAN training as a non-invasive watermark. This watermark is detectable in the generated images, tracing the specific quantum hardware used for training and providing strong proof of ownership. To enhance security, we propose training qGANs on multiple quantum hardware, embedding a complex watermark comprising the noise signatures of all training hardware, making it difficult for adversaries to replicate. A machine learning classifier is developed to extract this watermark, identifying the training hardware from the generated images, thereby validating the authenticity of the model. The watermark signature is robust even when inference occurs on different hardware. We achieve watermark extraction accuracy of 100% for single-hardware training and ~ 90% for multi-hardware training setups. We also obtain a validation accuracy of ~ 90% on both single-hardware and multi-hardware training setups in the presence of temporal variation of noise. This watermarking method can be extended to other quantum machine learning models due to the strong modulation of parameter evolution by quantum noise during training.

Гушанский Сергей Михайлович, Переверзев Владимир Андреевич

This article discusses the principles of quantum computing simulation using hardware approach. We describe a general mathematical model of a quantum computer; we show the method of mathematical modeling of quantum computation with optimization and a scheme of a hardware processing core in a quantum computing accelerator. The article gives a method of assessment of increasing productivity in the simulation of quantum computations using computing hardware core. The problems associated with the parallelization of computations on a hardware accelerator, simulating quantum computing were analyzed. The work lists the results of comparison of software and hardware simulation, as well as the dependence of the temporal evaluation of the number of qubits and parallel ALU in the computer-hardware accelerator

Harry Buhrman, Floor van de Pavert