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Journal of Applied Physics

A Multi-Aperture Cryogenic Storage Cell

J. Mundy, V. L. Newhouse

Published May 1, 1968• 1 citation

Abstract

Two types of superconducting memory cells are now being considered: the continuous-film memory and cryotron-switched storage loops. The former suffer from low cell operating range compared to cell-to-cell variation. The cryotron cells, although having a wider operating range, must be switched very rapidly to have a detectable output signal. A recent development in cryogenic sensing called ``Current Stretch'' has allowed more freedom in the design of superconducting memory cells. With current stretching the information is transformed to a persistent input current in a cryotron amplifier. The signal produced when the cell is switched is then proportional to the magnetic flux change rather than the rate of change of flux. This feature eliminates the usual memory requirements of fast-access current risetime, pickup noise cancellation, fast cell switching, and the need for a separate sense line with cryotron-accessed memories. A new class of cell which takes advantage of this technique will be described. It consists of a cryotron shunted across a loop, one side of which has a lower inductance and critical current than the other. If the cryotron is activated while current is injected into the cell, a persistent current is created in the loop. Cell-flux changes are detected through one of the cryotron access trees using current stretching. The operating tolerance of these cells is only limited by their geometry. They have no metal-to-metal contacts, use only three metal layers including the ground plane, need no sense line, no noise cancellation, and can be switched arbitrarily slowly. Cells can be fabricated as small as 10 mil2 and operating ranges as large as 40% have been observed. The cell speed is on the order of 50 nsec with a single crossover access cryotron.

DOI: 10.1063/1.1656622

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A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10[superscript -19] J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm ×7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.

A new vortex transitional NDRO memory cell has been proposed for use as a high-speed cache memory. The memory cell consists of two superconducting loops with one Josephson junction and a two-junction interferometer gate. The superconducting loop stores single-flux quantum. The interferometer gate operates as a sense gate. The memory cell employs a vortex transition in the superconducting loop for the writing and reading of data. The sense gate current margin increases to ±38% since the coupling magnetic flux is amplified by the vortex transition for nominally designed cell parameters. The memory cell operates with a ±33% address signal current margin. This paper describes the memory cell design and the dynamic behavior of computer simulations.

Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.

The talk is based on an overview which was published recently (1). For this reason, only an abstract is given here, which includes Later results not contained in the aforementioned overview. The presently-known Josephson memory cells store information as persistent currents in superconducting loops, or what is equivalent as a magnetic flux in the area of the ring. This method of storage is nonvolatile and has no power consumption in the storing state. In a superconducting ring system, the magnetic flux is quantized, and cells have been built which operate either with only one flux quantum, or with many of them. For the Latter cells with many flux quanta (ring cells), quite a number of designs exist. They have one or two Josephson junctions in the ring, which allow writing. An external junction which is controlled by the ring current serves for non-destructive reading of the information. The smallest cell realized had an area of 900 ?m2 with a 2 ?m minimum line width. Switching speed was ? 80 ps. Cells which store information as a single-flux quantum (single flux-quantum cells = SFQ cells) in the ring, usually contain two Josephson junctions used for reading and writing. Read-out in most of these cells is destructive, but methods of reading non-destructively have also been proposed. The smallest device made had an area of ? 150 ?m2 with a minimum line width of 2 ?m. The read signal had a rise time ? 100 ps.

We report the development of flux memory for use with superconducting circuits. This technology stores persistent currents in superconducting loops on-chip to be used to provide flux biasing for superconducting circuits, like qubits. We developed three types of flux memory and draw comparisons among them for circuit design. We demonstrate the utility of flux memory by using an in-situ flux detector and characterize each approach and further demonstrate that once flux is set in a memory cell, benchtop DC control sources can be powered off, leaving the on-chip flux bias in place. We propose that flux memory can be arranged in a two-dimensional configuration to multiplex control signals and reduce how line counts scale (N^2 devices -> 2N control lines), and our experimental results pave the path to the proposed scalability. We demonstrate the use of flux memory to flux bias a transmon qubit and show the tunability of the qubit state to a target frequency which remained stable on-chip for 20 hours.

A proposal vortex transitional nondestructive read-out Josephson memory cell is successfully fabricated and tested. The memory cell consists of two superconducting loops in which a single flux quantum is stored and a two-junction interferometer gate as a sense gate. The memory cell employs vortex transitions in the superconducting loops for writing and reading data. The vortex transitional memory operation of the cell contributes to improving its sense discrimination and operating margin. The memory cell is activated by two control signals without timing control signals. Memory cell chips have been fabricated using a niobium planarization process. A±21% address signal current margin and a ±33% sense gate current margin have been obtained experimentally. Successful memory operations of a cell driven by two-junction interferometer gates has been demonstrated. The single flux quantum operations of this memory cell makes it an attractive basic element for a high-speed cache memory.