Quantum Chip

Quentin Herr, M. S. Wire, Andrew D. Smith

We recently reported communication up to 60 Gb/s between digital superconductor chips mounted on a passive carrier, using a novel driver circuit that produces a double-flux-quantum pulse. Here, we answer various practical questions pertaining to chip-to-chip and on-chip communication in greater detail. On-chip, the traditional single-flux-quantum driver is adequate, although margins and bit error rate degrade significantly at the microstrip resonance frequency. Chip-to-chip, using the double-flux-quantum driver, shows little frequency dependence, in spite of 13% reduction of signal current in the chip-to-chip transitions. Appropriate microstrip impedance is in the range 4-8 /spl Omega/ for a 4 kA/cm/sup 2/ Josephson junction IC process. Data includes bit errors rates for pseudo-random data in the range 3-27 Gb/s.

Graham P. Collins

Masaaki Maezawa, Hirotake Yamamori, Alexandre Shoji

A novel approach to chip-to-chip communication for RSFQ technology is proposed. The main idea is to fabricate Josephson junctions on a substrate for multi-chip packaging, which equips the substrate as well as the chip with built-in active drivers and receivers. The driver on the chip is connected directly to the receiver on the substrate through a connector which can be considered as a lumped circuit element. Because the circuit is free from the impedance matching constraint, broadband chip-to-chip data transfer with wide operating margins will be realized. We have designed, simulated and optimized a chip-to-chip single flux quantum (SFQ) pulse transfer circuit. For a connector inductance of 20 pH, the bias current margins and the maximum throughput have been calculated to be /spl plusmn/24% and above 50 Gb/s, respectively.

Dipankar Bhattacharyya, Jyotirmoy Guha

Lang Li, Minglu Cai, Tao Wang +4 more

Quantum resources offer intrinsic randomness that is valuable for applications such as cryptography, scientific simulation, and computing. Silicon-based photonics chips present an excellent platform for the cost-effective deployment of next-generation quantum systems on a large scale, even at room temperature. Nevertheless, the potential susceptibility of these chips to hacker control poses a challenge in ensuring security for on-chip quantum random number generation, which is crucial for enabling extensive utilization of quantum resources. Here, we introduce and implement an on-chip source-device-independent quantum random number generator (SDI-QRNG). The randomness of this generator is achieved through distortion-free on-chip detection of quantum resources, effectively eliminating classical noise interference. The security of the system is ensured by employing on-chip criteria for estimating security entropy in a practical chip environment. By incorporating a photoelectric package, the SDI-QRNG chip achieves a secure bit rate of 146.2 Mbps and a bare chip rate of 248.47 Gbps, with all extracted secure bits successfully passing the randomness test. Our experimental demonstration of this chip-level SDI-QRNG shows significant advantages in practical applications, paving the way for the widespread and cost-effective implementation of room-temperature secure QRNG, which marks a milestone in the field of QRNG chips.

George Jaroszkiewicz