LDPC codes

Yuta Nakahara, Toshiyasu Matsushima

Spatially “Mt. Fuji” coupled (SFC) low density parity check (LDPC) codes are constructed as a chain of block LDPC codes. A difference between the SFC-LDPC codes and the original spatially coupled (SC) LDPC codes is code lengths of the underlying block LDPC codes. The code length of the block LDPC code at the middle of the chain is larger than that at the end of the chain. It is experimentally confirmed that the bit error probability in the error floor region of the SFC-LDPC code is lower than that of the SC-LDPC code whose code length and design rate are the same as those of the SFC-LDPC code. In this letter, we calculate the weight distribution of the SFC-LDPC code and try to explain causes of the low bit error rates of the SFC-LDPC code.

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz

Mohammad Gholami, Masoumeh Alinia

Low‐density parity‐check (LDPC) codes from affine permutation matrices , called APM‐LDPC codes, are a class of LDPC codes whose parity‐check matrices consist of zero matrices or APMs of the same orders. APM‐LDPC codes are not quasi‐cyclic (QC), in general. In this study, necessary and sufficient conditions are provided for an APM‐LDPC code to have cycles of length 2 l , l ≥ 2, and a deterministic algorithm is given to generate APM‐LDPC codes with a given girth. Unlike Type‐I conventional QC‐LDPC codes, the constructed ( J , L ) APM‐LDPC codes with the J × L all‐one base matrix can achieve minimum distance greater than ( J + 1)! and girth larger than 12. Moreover, the lengths of the constructed APM‐LDPC codes, in some cases, are smaller than the best known lengths reported for QC‐LDPC codes with the same base matrices. Another significant advantage of the constructed APM‐LDPC codes is that they have remarkably fewer cycle multiplicities compared with QC‐LDPC codes with the same base matrices and the same lengths. Simulation results show that the binary and non‐binary constructed APM‐LDPC codes with lower girth outperform QC‐LDPC codes with larger girth.

Alexios Balatsoukas‐Stimming

Luiza R. Medova, Pavel S. Rybin, Ivan V. Filatov

In this paper we propose a simulation system for LDPC codes implemented on a field-programmable gate array device. The presented system includes an LDPC encoder, Gaussian noise generator and an LDPC decoder. An LDPC encoder and decoder are fully flexible and support different constructions of LDPC codes. It makes possible to obtain performance curves of a large number of LDPC codes and analyse their properties. We have found that the LDPC code proposed in [1] has an error floor higher than the LDPC code proposed by the experimental specification CCSDS 231.1-O-l. We have evaluated the performance of 2250 (128,256) LDPC codes with our simulation system and have found an LDPC code that outperforms the LDPC code from the experimental specification CCSDS 231.1-O-l.