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Springer proceedings in physics

FPGA Implementation of Outer Decoders for Sequential Decoder of Polar Codes

Nikita Makarov, Aleksei E. Krylov, Рашич Андрей Валерьевич, Tan Ngoc Nguyen

Published Jan 1, 2022• 0 citations
Publisher
DOI
10.1007/978-3-030-81119-8_21

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This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N1N2) can be divided into two parts: N1SC decoders of length N2and a single SC decoder of length N1. While the N1decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N1of N, and we show that an appropriate choice of N1yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.
Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.