Serial Sum-Product Architecture for Low-Density Parity-Check Codes
Ruwan Ratnayake, Erich F. Haratsch, Gu-Yeon Wei
A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to check node messages sequentially, while the check node computations are broken up into several steps and computed on the fly. This bit node centric architecture requires considerably less memory compared to other serial architectures, including the check node centric architecture.
International Conference on Computer Communications and Networks (ICCCN)•Aug 1, 2007•1 citation