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IEICE Technical Report; IEICE Tech. Rep.

Performance Evaluation of a Combination of Sum-Product and Two-bit Bit Flipping Decoding Algorithms

Koh Matsushita, Hiroshi Kamabe

Published Feb 28, 2013• 0 citations
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In this paper we present Low Density Parity Check decoding algorithm that assemble two different algorithms: Sum-Product and Bit-Flipping; we denote Bit Flipping-Sum Product Algorithm (BFSP). To reduce the bit error rate, we perform the Bit-Flipping algorithm after the Sum-Product algorithm. Simulation results over an additive white Gaussian channel show that the error performance of a LDPC codes with Bit Flipping-Sum Product decoding is within 0.2 dB of the standard Sum-Product decoding algorithms. Furthermore, the decoding complexity of the proposed BFSP algorithm is maintained at the same level as that of the standard Sum-Product algorithm.

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VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes

Junho Cho, Jonghong Kim, Wonyong Sung

VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.

IEEE Transactions on Circuits and Systems I Regular Papers•May 1, 2010•12 citations
In this paper, a new algorithm called Reliability Ratio Weighted Bit Flipping-Sum Product (RRWBFSP) decoding is proposed for low-density parity-check codes.The new algorithm combines two different algorithms, Sum Product [4] and Reliability Ratio Weighted Bit Flipping [6].The results of the simulation show that the new algorithm achieves a 0.34 dB performance gain over of the standard Sum-Product decoding algorithms.Furthermore, RRWBFSP algorithm has almost the same computational complexity compared to the standard Sum-Product algorithm.
In this paper we present Low Density Parity Check decoding algorithm that assemble two different algorithms: Sum-Product and Bit-Flipping; we denote Bit Flipping-Sum Product Algorithm (BFSP). To reduce the bit error rate, we perform the Bit-Flipping algorithm after the Sum-Product algorithm. Simulation results over an additive white Gaussian channel show that the error performance of a LDPC codes with Bit Flipping-Sum Product decoding is within 0.2 dB of the standard Sum-Product decoding algorithms. Furthermore, the decoding complexity of the proposed BFSP algorithm is maintained at the same level as that of the standard Sum-Product algorithm.
VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.