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International Symposium on I/V Communications and Mobile Network (ISIVC)

Bit Flipping-Sum Product Algorithm for regular LDPC codes

Rachid El Alami, Cheikh Bamba Gueye, Mohammed Boussetta, Mohcine Zouak, Mostafa Mrabti

Published Sep 1, 2010• 3 citations
Publisher

Abstract

In this paper we present Low Density Parity Check decoding algorithm that assemble two different algorithms: Sum-Product and Bit-Flipping; we denote Bit Flipping-Sum Product Algorithm (BFSP). To reduce the bit error rate, we perform the Bit-Flipping algorithm after the Sum-Product algorithm. Simulation results over an additive white Gaussian channel show that the error performance of a LDPC codes with Bit Flipping-Sum Product decoding is within 0.2 dB of the standard Sum-Product decoding algorithms. Furthermore, the decoding complexity of the proposed BFSP algorithm is maintained at the same level as that of the standard Sum-Product algorithm.

DOI
10.1109/isvc.2010.5656207

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In this paper we present Low Density Parity Check decoding algorithm that assemble two different algorithms: Sum-Product and Bit-Flipping; we denote Bit Flipping-Sum Product Algorithm (BFSP). To reduce the bit error rate, we perform the Bit-Flipping algorithm after the Sum-Product algorithm. Simulation results over an additive white Gaussian channel show that the error performance of a LDPC codes with Bit Flipping-Sum Product decoding is within 0.2 dB of the standard Sum-Product decoding algorithms. Furthermore, the decoding complexity of the proposed BFSP algorithm is maintained at the same level as that of the standard Sum-Product algorithm.
In this paper, a new algorithm called Reliability Ratio Weighted Bit Flipping-Sum Product (RRWBFSP) decoding is proposed for low-density parity-check codes.The new algorithm combines two different algorithms, Sum Product [4] and Reliability Ratio Weighted Bit Flipping [6].The results of the simulation show that the new algorithm achieves a 0.34 dB performance gain over of the standard Sum-Product decoding algorithms.Furthermore, RRWBFSP algorithm has almost the same computational complexity compared to the standard Sum-Product algorithm.
In this paper, we develop the density evolution of bit-flipping algorithm (BFA) for regular low-density parity-check (LDPC) codes and analyze the evolution of probability density for the bit-decision error. In contrast to the sum-product algorithm (SPA) and min-sum algorithm (MSA), the density evolution for BFA has remained untouched, which motivates this work. In the developed density evolution for BFA, we first introduce a state variable which is a function of bit-decision result and the flipping function value at each iteration. Then, the state probability is derived, with which the density of bit-decision error is obtained. To confirm the derivations, we design regular LDPC codes and compare the empirical evaluations of bit-error rates and the derived probability of bit-decision errors.
Low-density parity-check (LDPC) codes are a subclass of linear block codes. These codes have parity-check matrices in which the ratio of the non-zero elements to all elements is low. This property is exploited in defining low complexity decoding algorithms. Low-density parity-check codes have good distance properties and error correction capability near Shannon limits. In this thesis, the sum-product and the bit-flip decoding algorithms for low-density parity-check codes are implemented on Intel Pentium M 1,86 GHz processor using the software called MATLAB. Simulations for the two decoding algorithms are made over additive white gaussian noise (AWGN) channel changing the code parameters like the information rate, the blocklength of the code and the column weight of the parity-check matrix. Performance comparison of the two decoding algorithms are made according to these simulation results. As expected, the sum-product algorithm, which is based on soft-decision decoding, outperforms the bit-flip algorithm, which depends on hard-decision decoding. Our simulations show that the performance of LDPC codes improves with increasing blocklength and number of iterations for both decoding algorithms. Since the sum-product algorithm has lower error-floor characteristics, increasing the number of iterations is more effective for the sum-product decoder compared to the bit-flip decoder. By having better BER performance for lower information rates, the bit-flip algorithm performs according to the expectations; however, the performance of the sum-product decoder deteriorates for information rates below 0.5 instead of improving. By irregular construction of LDPC codes, a performance improvement is observed especially for low SNR values.
Based on decoding performance, complexity and latency of finite-geometry low-density parity-check (LDPC) codes, an efficient decoding algorithm is proposed. The algorithm is a hybrid bit-flipping (BF)/majority-logic (MLG) algorithm. In the algorithm, there are two stages. At the first stage, a code is decoded with bit-flipping (BF) with a small fixed number of iterations. Then the output from bit-flipping (BF) decoder is decoded by majority-logic (MLG) decoding. And in bit-flipping (BF) decoding, a new method is used to find the least reliable position. In the hybrid algorithm, there aren't real operations. Simulation results show that the algorithm provides 0.3dB coding gain over weight bit-flipping (WBF) decoding, and within 1 dB away from sum-product algorithm (SPA) decoding.
Low Density Parity Check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. In many digital communication systems, these codes have strong competitors of turbo codes for error control. LDPC codes performance depends on the excellent design of parity check matrix and many diverse research methods have been used by different study groups to evaluate the performance. Unlike many other classes of codes, LDPC codes are already equipped with a fast, probabilistic decoding algorithm. This makes LDPC codes not only attractive from a theoretical point of view, but also very suitable for practical applications. This paper throws hard decision and soft decision algorithm of LDPC. The hard decision algorithm contains Bit flipping algorithm and Soft decoding algorithm contains Sum product algorithm which is used to correct burst error. Sum Product algorithm is also called as belief propagation. Bit flipping and Sum Product algorithms are explained and can be implemented for the generated parity check matrix of (1016x508) for LDPC code with code rate 1/2.
The Bit-Flipping (BF) algorithm is considered as a hard decoding method for LDPC codes. It is much simpler than the probabilistic methods like Sum Product Algorithm (SPA), and can be efficiently implemented by electronic circuits. In this paper, we propose a new Bit Flipping algorithm for Low-Density Parity-Check codes (LDPC) called Single Bit-Flipping (SBF). Compared to the Gallager Bit-Flipping algorithm, the proposed algorithm employs criteria of flipping single bit chosen carefully. This method eliminates the risk for flipping more than one bit at a time that can induce additional error bits and propagate the errors to the later iterations. We present some results obtained by applying this new method that provides a gain in performance in comparison to the standard Gallager Bit-Flipping with low complexity.