Reversible logic is leading area in power consumption.Based on its application, its emerging trend in power consumption.In ideal situations, reversible circuit yield nil power.Different methods of multiplier optimized in this paper.Like quantum computers, multipliers required to develop computational units.In the paper, two different methods of multiplier developed with very large bit width.Based on partial products hierarchical method is developed.Another method is Karatsuba's algorithm developed based on divide and conquers method.Finally, we compare the results of both two methods.The projected reversible multipliers are enhanced in terms of quantum cost, number of constant inputs, number of garbage outputs and complexity in hardware.In nanotechnology applications this multiplier can be used to construct complex system.
Reversible logic is leading area in power consumption.Based on its application, its emerging trend in power consumption.In ideal situations, reversible circuit yield nil power.Different methods of multiplier optimized in this paper.Like quantum computers, multipliers required to develop computational units.In the paper, two different methods of multiplier developed with very large bit width.Based on partial products hierarchical method is developed.Another method is Karatsuba's algorithm developed based on divide and conquers method.Finally, we compare the results of both two methods.The projected reversible multipliers are enhanced in terms of quantum cost, number of constant inputs, number of garbage outputs and complexity in hardware.In nanotechnology applications this multiplier can be used to construct complex system.
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
Reversible logic is now employed in low-power CMOS circuits, optical data processing, DNA calculations, biological studies, quantum circuits, and nanotechnology.When building quantum computers, for example, the use of reversible logic is unavoidable.The structure of a reversible logic circuit is far more complex than that of an irreversible logic circuit.The multiplication operation is regarded as one of the most crucial in the ALU unit.In this paper, the Wallace tree method is utilized to minimize the depth of circuits in 8x 8 reversible unsigned multiplier circuits.The proposed design is an attempt to enhance design factors including the number of gates, garbage outputs, constant inputs, and quantum cost for an 8-bit Wallace Tree multiplier using reversible logic.The Proposed design offers 27% less quantum cost compared to the existing 8-bit Wallace tree multiplier design.
Reversible logic is one of the stepping stones in low power circuit design. Due to low power consumption and minimum bit loss features, future quantum computing devices are estimated to be reversible. Compared to addition, multiplication is a step further in the ladder of abstraction. It is the manifestation of a pattern generation system capable of representing 3-D patterns and transforming them by rotation, projection, reflection etc. The use of reversible logic in this field can reduce the wastage of energy, power and improve many factors. In this paper, an efficient multiplication algorithm has been proposed which is a modification of conventional shift-and-add multiplication method. Implementing proposed algorithm two reversible multiplier circuit has been proposed. For producing partial product, Peres gate has been used for the first design and Toffoli gate for the second design. Both of the circuits use Peres gate as Half-Adder and HNG gate as Full-Adder for addition of partial products. The first design is improved radically in terms of quantum cost, delay and the second design is notably improved in terms of transistor count and hardware complexity compared to the existing best known multipliers.
In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.
Reversible logic design is one of the emerging trends in recent years as it is good for low power design. A good number of design methods for reversible multipliers were proposed earlier. In this paper, two bit reversible multiplier was designed using Reed-Muller expressions, and this new reversible multiplier was used to design 4-bit reversible multiplier. The results save 16.9% of quantum cost (QC), 38.5% of garbage outputs (GOs) and 10.7% of constant inputs (CIs) compared to earlier designs. The simulations are done on Xilinx 10.1 and are presented. The methodology is extended for the design of 8-bit and 16-bit multipliers and the reversible logic metrics were presented for different bit lengths.