This work aims to find signal sequences that implement high-quality logic gates for single GaAs qubits in a quantum computer. To achieve that an optimization of the gate quality with a scalable electronic architecture in mind is done. In addition, a behavioral model of the qubit and the control electronics in the Q-Interface is implemented. The electronic model includes typical integrated circuit impairments such as process variations and parasitic capacitors. While the initial quality of the optimized gates is high, simulations with the implemented model show partly large quality reductions for some impairments. A major quality loss is for example caused by parasitic capacitors, but some non-ideal effects can be mitigated through pre-distortion, among others.
This work aims to find signal sequences that implement high-quality logic gates for single GaAs qubits in a quantum computer. To achieve that an optimization of the gate quality with a scalable electronic architecture in mind is done. In addition, a behavioral model of the qubit and the control electronics in the Q-Interface is implemented. The electronic model includes typical integrated circuit impairments such as process variations and parasitic capacitors. While the initial quality of the optimized gates is high, simulations with the implemented model show partly large quality reductions for some impairments. A major quality loss is for example caused by parasitic capacitors, but some non-ideal effects can be mitigated through pre-distortion, among others.
A key ingredient for fault-tolerant quantum computers are sufficiently accurate logic gates on single and multiple qubits in the presence of decohering noise. In this thesis, we theoretically develop and experimentally demonstrate such high-fidelity quantum gates for semiconductor-based quantum computing. Specifically, we consider a qubit encoded in the singlet and one triplet state of two electron spins in GaAs. While its potential for optical coupling makes GaAs an attractive material, highly auto-correlated magnetic field noise from fluctuating nuclear spins leads to considerably lower coherence times than for Si-based devices, where nuclear spins can be removed by isotopic purification. In addition to noise, the control methods used in earlier experiments are based on unrealistic approximations. For these reasons, fidelities well above 99 %, as required by current quantum error correction (QEC) schemes, have not been obtained before this thesis. To tackle these issues, we extend the filter function formalism to describe quantum gates and processes in the presence of experimentally relevant non-Markovian noise. Since this formalism can consider all relevant noise sources in a computationally efficient manner, it can be used to find optimal control pulses by numerical optimization, leading to predicted single-qubit gate fidelities of 99.9 %. Furthermore, we deal with the considerable control challenges associated with this qubit type by experimental calibration of the optimized control pulses. To this end, we extend our previous experimental gate set calibration (GSC) routine to remove systematic gate errors on an arbitrary number of qubits. We apply the numerically optimized single-qubit control pulses to our GaAs sample and experimentally calibrate them with GSC. This procedure yields an average gate fidelity of 99.50 ± 0.04 % and a low leakage rate of 0.13 ± 0.03 % out of the computational subspace, characterized by randomized benchmarking. We also optimize realistic two-qubit control pulses, considering current control hardware as well as interqubit Coulomb and exchange coupling that cannot be fully turned off. Using measured noise spectra, we show that two-qubit gate fidelities of 99.90 % can be reached in GaAs, while 99.99 % can be achieved in Si. These results demonstrate that high-fidelity gates can be realized even in the presence of nuclear spins as in GaAs.
In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.
Spin qubits are very valuable and scalable candidates in the area of quantum computation and simulation applications. In the last decades, they have been deeply investigated from a theoretical point of view and realized on the scale of few devices in the laboratories. In semiconductors, spin qubits can be built confining the spin of electrons in electrostatically defined quantum dots. Through this approach, it is possible to create different implementations: single electron spin qubit, singlet–triplet spin qubit, or a three-electron architecture, e.g., the hybrid qubit. For each qubit type, we study the single qubit rotations along the principal axis of Bloch sphere including the mandatory non-idealities of the control signals that realize the gate operations. The realistic transient of the control signal pulses are obtained by adopting an appropriate low-pass filter function. In addition. the effect of disturbances on the input signals is taken into account by using a Gaussian noise model.
Abstract Two-qubit gates are important components of quantum computing. However, unwanted interactions between qubits (so-called parasitic gates) can be particularly problematic and degrade the performance of quantum applications. In this work, we present two software methods to mitigate parasitic two-qubit gate errors. The first approach is built upon the Cartan’s KAK decomposition and keeps the original unitary decomposition for the error-free native two-qubit gate. It counteracts a parasitic two-qubit gate by only applying single-qubit rotations and therefore has no two-qubit gate overhead. We show the optimal choice of single-qubit mitigation gates. The second approach applies a numerical optimisation algorithm to re-compile a target unitary into the error-parasitic two-qubit gate plus single-qubit gates. We demonstrate these approaches on the CPhase-parasitic iSWAP-like gates. The KAK-based approach helps decrease unitary infidelity by a factor of 3 compared to the noisy implementation without error mitigation. When arbitrary single-qubit rotations are allowed, recompilation could completely mitigate the effect of parasitic errors but may require more native gates than the KAK-based approach. We also compare their average gate fidelity under realistic noise models, including relaxation and depolarising errors. Numerical results suggest that different approaches are advantageous in different error regimes, providing error mitigation guidance for near-term quantum computers.
Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cryogenic chamber. However, these systems must scale to support millions of qubits. While scaling up the underlying quantum processor is already exceptionally challenging, building the electronics required to interface such a large-scale processor is just as relevant and arduous.
Spin-based quantum architectures offer a promising route toward scalable and practical quantum computing owing to their long coherence times, high-fidelity gate operations, and compatibility with established semiconductor fabrication processes. This work focuses on the design, decomposition, and simulation of fundamental multi-qubit logic gates on spin-based architectures. An optimized CNOT gate decomposition is presented, achieving a 36.36% reduction in elementary operations, verified through quantum circuit simulation. Furthermore, a resource-efficient Toffoli (CCNOT) gate is developed, yielding a 38% reduction in elementary gates and demonstrating improved T-depth efficiency. Finally, a four-qubit circuit example is presented, illustrating the scalability of the pseudocode and validating the correctness of the proposed approach.