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International Conference on Computer Science and Engineering (UBMK)

PYNQ-Based Rapid FPGA Implementation of Quantum Key Distribution

Yigit Bilgin, Shewit W. Tesfay, Seckin Ipek, H. Fatih Uğurdağ, Kadir Durak, Sezer Gören

Published Sep 15, 2021• 2 citations
Publisher

Abstract

In this paper, we present a real-time Quantum Key Distribution (QKD) implementation on Field Programmable Gate Arrays (FPGAs) for secure communication. We propose a novel methodology with a Python-based programming interface for rapid development on FPGA. Our methodology revolves three phases of development. In the first phase, a reference model of an entangled photon source and the proposed QKD system are developed in Python. Next, the reference model is passed through a thorough verification phase. In the second phase, the reference model is implemented on the Processing System (PS) part of the FPGA. Finally in the third phase, the computationally intensive part of the QKD architecture is off-loaded on to the Programmable Logic (PL) part of the FPGA for acceleration. We employ PYNQ framework in our QKD development and successfully combine the convenience of Python productivity with FPGA based acceleration.

DOI
10.1109/ubmk52708.2021.9558886

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In this paper, we present a real-time Quantum Key Distribution (QKD) implementation on Field Programmable Gate Arrays (FPGAs) for secure communication. We propose a novel methodology with a Python-based programming interface for rapid development on FPGA. Our methodology revolves three phases of development. In the first phase, a reference model of an entangled photon source and the proposed QKD system are developed in Python. Next, the reference model is passed through a thorough verification phase. In the second phase, the reference model is implemented on the Processing System (PS) part of the FPGA. Finally in the third phase, the computationally intensive part of the QKD architecture is off-loaded on to the Programmable Logic (PL) part of the FPGA for acceleration. We employ PYNQ framework in our QKD development and successfully combine the convenience of Python productivity with FPGA based acceleration.
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Quantum key distribution (QKD) provides a secure and effective way of exchanging cryptographic symmetric keys without the possibility of an eavesdropper being undetected. The transmission and detection of the quantum states at the physical layer is the first step to defining a common source of entropy, where both parties will extract a raw key. Over the last few years, continuous variable quantum key distribution (CV-QKD) protocols have become an attractive technology for QKD, providing a low-cost solution that can be easily integrated with the current optical network devices and infrastructure. Unlike other QKD technologies, a CV protocol requires complex and highly computationally demanding digital signal processing (DSP) operations. In that sense, parallel computation tools such as field programmable gate arrays (FPGAs) represent a key element for the practical implementation of this quantum technology and to scale its performance in terms of distance and secret key rate indicators. This work presents an FPGA-based implementation of the physical layer of a CV-QKD transmitter. The proposed architecture and employed protocols are described, and hardware implementation aspects are discussed, including resource occupation analysis, configuration parameters, and timing issues.
For high-speed quantum key distribution systems, error reconciliation is often the bottleneck affecting system performance. By exchanging common information through a public channel, the identical key can be generated on both communicating sides. However, the necessity to eliminate disclosed bits for security reasons lowers the final key rate. To improve this key rate, the amount of disclosed bits should be minimized. In addition, decreasing the time spent on error reconciliation also improves the key rate. In this paper, we introduce a practical method for expeditious error reconciliation implemented in a field programmable gate array for a discrete variable quantum key distribution system, and illustrate the superiority of this method to other similar algorithms running on a PC. Experimental results demonstrate the rapidity of the proposed protocol.
As threats in the maritime domain diversify, securing data transmission becomes critical for underwater wireless networks designed for the surveillance of critical infrastructure and maritime border protection. This has sparked interest in underwater Quantum Key Distribution (QKD). In this paper, we present an FPGA-based real-time implementation of an underwater QKD system based on the BB84 protocol. The QKD unit is built on a hybrid computation system consisting of an FPGA and an on-board computer (OBC) interfaced with optical front-ends. A real-time photon counting module is implemented on FPGA. The transmitter and receiver units are powered with external UPS and all system parameters can be monitored from the connected computers. The system is equipped with a visible laser and an alignment indicator to validate successful manual alignment. Secure key distribution at a rate of 100 qubits per second was successfully tested over a link distance of 7 meters.
The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process.
Abstract This paper presents a new hardware implementation of the quantum key distributed cryptography protocol using Field Programmable Gate Array (FPGA). In many security applications, the software implementations of key distribution algorithms are slow and inefficient. In order to solve this problems, new hardware architecture was proposed to speed up the performance and flexibility of key distribution algorithms. The concurrent computing designs quantum key distribution protocol with reducing the hardware area, producing a high throughput and low latency. It also showed high speed processing and consumed low power. An efficient hardware architectural model for quantum key distribution protocol was developed using very high-speed integrated circuit hardware description language (VHDL). This hardware designed to be used with any quantum key distribution protocol to distribution the secret key securely. The hardware implemented and test with Spartan-3 FPGA board and the results show a throughput of 8 Mbps and efficiency of 1.6 Mbps/slice.