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Designing Quantum Controls Efficiently

Alicia B Magann

Published Jan 1, 2021• 0 citations
OpenAlex

Abstract

a) Pulse level (b) Circuit level

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Quantum pulse serves as the machine language of superconducting quantum devices, which needs to be synthesized and calibrated for precise control of quantum operations. However, existing pulse control systems suffer from the dilemma between long synthesis latency and inaccuracy of quantum control systems. compute-in-CPU synthesis frameworks, like IBM Qiskit Pulse, involve massive redundant computation during pulse calculation, suffering from a high computational cost when handling large-scale circuits. On the other hand, field-programmable gate array (FPGA)-based synthesis frameworks, like QuMA, faces inaccurate pulse control problem. In this article, we propose both compute-in-CPU and all-in-FPGA solutions to collaboratively solve the latency and inaccuracy problem. First, we propose QPulseLib, a novel compute-in-CPU library with reusable pulses that can directly provide the pulse of a circuit pattern. To establish this library, we transform the circuit and apply convolutional operators to extract reusable patterns and precalculate their resultant pulses. Then, we develop a matching algorithm to identify such patterns shared by the target circuit. Experiments show that QPulseLib achieves$158.46\times $and$16.03\times $speedup for pulse calculation, compared to Qiskit Pulse and AccQOC. Moreover, we extend the design as a fast and precise all-in-FPGA pulse control approach using near-quantum cache design, SmartQCache. To be specific, we employ a two-level cache to hold reusable pulses of frequently-used circuit patterns. Such a design enables pulse prefetching in near-quantum peripherals, dramatically reducing the end-to-end synthesis latency. To achieve precise pulse control, SmartQCache incorporates duration optimization and pulse sequence calibration to mitigate the execution errors from imperfect hardware, crosstalk, and time shift. Experimental results demonstrate that SmartQCache achieves$294.37\times $and$145.43\times $speedup in pulse synthesis compared to Qiskit Pulse and AccQOC. It also reduces the pulse inaccuracy by$1.27\times $compared to QuMA.

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quant-pharXiv:2602.05154•Feb 6, 2026•0 citations
Quantum pulse serves as the machine language of superconducting quantum devices, which needs to be synthesized and calibrated for precise control of quantum operations. However, existing pulse control systems suffer from the dilemma between long synthesis latency and inaccuracy of quantum control systems. compute-in-CPU synthesis frameworks, like IBM Qiskit Pulse, involve massive redundant computation during pulse calculation, suffering from a high computational cost when handling large-scale circuits. On the other hand, field-programmable gate array (FPGA)-based synthesis frameworks, like QuMA, faces inaccurate pulse control problem. In this article, we propose both compute-in-CPU and all-in-FPGA solutions to collaboratively solve the latency and inaccuracy problem. First, we propose QPulseLib, a novel compute-in-CPU library with reusable pulses that can directly provide the pulse of a circuit pattern. To establish this library, we transform the circuit and apply convolutional operators to extract reusable patterns and precalculate their resultant pulses. Then, we develop a matching algorithm to identify such patterns shared by the target circuit. Experiments show that QPulseLib achieves$158.46\times $and$16.03\times $speedup for pulse calculation, compared to Qiskit Pulse and AccQOC. Moreover, we extend the design as a fast and precise all-in-FPGA pulse control approach using near-quantum cache design, SmartQCache. To be specific, we employ a two-level cache to hold reusable pulses of frequently-used circuit patterns. Such a design enables pulse prefetching in near-quantum peripherals, dramatically reducing the end-to-end synthesis latency. To achieve precise pulse control, SmartQCache incorporates duration optimization and pulse sequence calibration to mitigate the execution errors from imperfect hardware, crosstalk, and time shift. Experimental results demonstrate that SmartQCache achieves$294.37\times $and$145.43\times $speedup in pulse synthesis compared to Qiskit Pulse and AccQOC. It also reduces the pulse inaccuracy by$1.27\times $compared to QuMA.
Current quantum programs are mostly synthesized and compiled on the gate-level, where quantum circuits are composed of quantum gates. The gate-level workflow, however, introduces significant redundancy when quantum gates are eventually transformed into control signals and applied on quantum devices. For superconducting quantum computers, the control signals are microwave pulses. Therefore, pulse-level optimization has gained more attention from researchers due to their advantages in terms of circuit duration. Recent works, however, are limited by their poor scalability brought by the large parameter space of control signals. In addition, the lack of gate-level "knowledge" also affects the performance of pure pulse-level frameworks. We present a hybrid gate-pulse model that can mitigate these problems. We propose to use gate-level compilation and optimization for "fixed" part of the quantum circuits and to use pulse-level methods for problem-agnostic parts. Experimental results demonstrate the efficiency of the proposed framework in discrete optimization tasks. We achieve a performance boost at most 8% with 60% shorter pulse duration in the problem-agnostic layer.
QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 100x faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA.