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International Journal of Advanced Research in Science Communication and Technology

Modular Adders Based on Reversible Circuits

Prof. Bhavya V, Prof. Asha R, Jagadeesh B V, Y Adithya, K P Apoorva, Basamma N Biradar

Published Jul 24, 2021• 0 citations
Publisher

Abstract

Reversible logic is a computing model which has gained remarkable heed in recent years due to its properties that lead to ultra power and reliable circuits. Reversible circuits are key, for quantum computing. In this work we propose the usage of modular adders, in particular modular 2n-1 adders, with the use of reversible logic. Analysis comparison with normal adders and modular adders with reversible gates.

DOI
10.48175/ijarsct-1772

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Reversible logic is a computing model which has gained remarkable heed in recent years due to its properties that lead to ultra power and reliable circuits. Reversible circuits are key, for quantum computing. In this work we propose the usage of modular adders, in particular modular 2n-1 adders, with the use of reversible logic. Analysis comparison with normal adders and modular adders with reversible gates.
The futuristic computing is desired to be more power full with low-power consumption.That is why quantum computing has been a key area of research for quite some time and is getting more and more attention.Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times.Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance.In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer.The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations.The quantum costs of these designs are comparable.Many of the implemented micro-operations are not seen in previous literatures.The performances of the proposed circuits are compared with existing designs wherever available.
Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2k, 2p-1}. Modulo 2n-1, 2n, and 2n+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2n-1, 2n+k, 2n+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.
Reversible logic is gaining importance in recent years largely due to its property of low power consumption.It has a wide range of applications which include advance computing, low power CMOS, optical information processing, quantum computing, DNA cryptography and nanotechnology.Reversible gates are the building blocks of quantum computation.This paper presents an optimized parallel binary adder/subtractor using existing reversible gates which is further used to implement a novel circuit capable of performing modulo operation.All circuits have been modeled and verified using Verilog and Modelsim.An overall analysis of the modulo circuit and a comparative study of the proposed parallel adder/subtractor with respect to previous designs in terms of the number of gates, number of garbage outputs and quantum costs is presented.
One of the major problems in designing highly compact digital systems is the rate of power consumption and internal heat generated by the loss of information during the computation. The tendency of current circuit design technologies is towards Nanoscale. Quaternary reversible logic is an emerging technology for the future designing of the quantum systems since quantum reversible circuits can be realized in Nanoscales. The adder building block is an essential part of any computer system. This block must be designed efficiently. We proposed a new quaternary quantum reversible half adder with the quantum cost of 17 and a quaternary quantum reversible full adder with a quantum cost of 23. For the first time in the literature, we report that we proposed quaternary quantum reversible half adder as well as full adder with an optimum number of constant inputs. As the circuit lines in the domain of quantum computation are considered to be a very limited resource, the achievements in this paper are promising. The proposed circuits are efficient in terms of all figures of merits in comparison to the existing counterparts. To design these adder circuits, we used 1-qudit and 2-qudit quaternary gates.
The ternary quantum circuit is very useful in arithmetic and logic operations. This circuit has several advantages as it reduces power dissipation, step time, etc. Adder circuit is the main block of various computing units and for several other complex computer designs. In this current paper, we have used generalized ternary gate (GTG) and reversible gates for the synthesis of reversible half adder and a full adder circuits. The presented designs offer reduced constant inputs and less quantum cost, compared to existing designs. Our proposed design allows a reduction of 40% of the cost and 25% of the number of gates used.