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The Japan Society of Applied Physics

Evaluation of magnetically-coupling SFQ driver/receiver circuit fabricated using Nb 10 kA/cm 2 processes

Yuta Somei, Hiroshi Shimada, Yoshinao Mizugaki

Published Jan 26, 2021• 0 citations
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Enhanced operation frequencies of bipolar double-flux-quantum amplifiers fabricated using 10 kA cm −2 Nb/AlO x /Nb integration process

Yuta Somei, Hiroshi Shimada, Yoshinao Mizugaki

Abstract We have demonstrated digital-to-analog (D/A) operations using single-flux-quantum (SFQ) pulse-frequency modulation (PFM) D/A converters for future AC voltage standards. In this paper, for the improvement of SFQ-PFM D/A converters, we investigated a double-flux-quantum amplifier (DFQA) and a magnetically-coupling SFQ driver/receiver circuit (MC-SFQ-DR) fabricated using a 10 kA cm −2 Nb/AlO x /Nb integration process. The critical current density J c of 10 kA cm −2 was four times larger than that of the integration process we had used. A DFQA and an MC-SFQ-DR included unshunted Josephson junctions, and therefore, it was unclear if the high- J c process improved their performances. We measured test chips cooled in a liquid helium bath. The maximum input voltages for a +20 fold and a −20 fold DFQA were 147 and 126 μ V, for which the corresponding Josephson frequencies were 70.9 and 61.1 GHz. It was confirmed that the operation frequencies of the DFQAs and MC-SFQ-DR were improved approximately two-fold.

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Output Interface With Latching Driver for LTS-SFQ Circuits

Tsunehiro Hato, Masahiro Horibe, H. Wakana +2 more

We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.

IEEE Transactions on Applied Superconductivity•Mar 1, 2005•5 citations
Abstract We have demonstrated digital-to-analog (D/A) operations using single-flux-quantum (SFQ) pulse-frequency modulation (PFM) D/A converters for future AC voltage standards. In this paper, for the improvement of SFQ-PFM D/A converters, we investigated a double-flux-quantum amplifier (DFQA) and a magnetically-coupling SFQ driver/receiver circuit (MC-SFQ-DR) fabricated using a 10 kA cm −2 Nb/AlO x /Nb integration process. The critical current density J c of 10 kA cm −2 was four times larger than that of the integration process we had used. A DFQA and an MC-SFQ-DR included unshunted Josephson junctions, and therefore, it was unclear if the high- J c process improved their performances. We measured test chips cooled in a liquid helium bath. The maximum input voltages for a +20 fold and a −20 fold DFQA were 147 and 126 μ V, for which the corresponding Josephson frequencies were 70.9 and 61.1 GHz. It was confirmed that the operation frequencies of the DFQAs and MC-SFQ-DR were improved approximately two-fold.
We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.