Abstract Josephson superconducting qubits and parametric amplifiers are prominent examples of superconducting quantum circuits that have shown rapid progress in recent years. As such devices become more complex, the requirements for reproducibility of their electrical properties across a chip are being tightened. Critical current of the Josephson junction Ic is the essential electrical parameter in a chip. So, its variation is to be minimized. According to the Ambegaokar–Baratoff formula, critical current is related to normal-state resistance, which can be measured at room temperature. In this study, we focused on the dominant source of non-uniformity for the Josephson junction critical current–junction area variation. We optimized Josephson junction fabrication process and demonstrated resistance variation of 9.8–4.4% and 4.8–2.3% across 22 × 22 mm2 and 5 × 10 mm2 chip areas, respectively. For a wide range of junction areas from 0.008 to 0.12 μm2, we ensure a small linewidth standard deviation of 4 nm measured over 4500 junctions with linear dimensions from 80 to 680 nm. We found that the dominate source of junction area variation limiting
Ic I c reproducibility is the imperfection of the evaporation system. The developed fabrication process was tested on superconducting highly coherent transmon qubits (T1 > 100 μs) and a nonlinear asymmetric inductive element parametric amplifier.
Abstract Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current I c variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ≡ σ I c / I c ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown σ I c / I c = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having σ I c / I c < 1.0% (equivalent to σ f / f < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.
The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale
Al/AlOx/Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate
Al/AlOx/Al junction fabrication with the critical current variation (
σ/Ic) less than 3.9% (from
150×200 to
150×600 nm2 area) and 7.7% (for
100×100 nm2 area) over
20×20 mm2 chip. Finally, we fabricate separately three
5×10 mm2 chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubit on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.
Abstract Decoherence in quantum bits (qubits) is a major challenge for realizing scalable quantum computing. One of the primary causes of decoherence in qubits and quantum circuits based on superconducting Josephson junctions is the critical current fluctuation. Many efforts have been devoted to suppressing the critical current fluctuation in Josephson junctions. Nonetheless, the efforts have been hindered by the defect-induced trapping states in oxide-based tunnel barriers and the interfaces with superconductors in the traditional Josephson junctions. Motivated by this, along with the recent demonstration of 2D insulator h -BN with exceptional crystallinity and low defect density, we fabricated a vertical NbSe 2 / h -BN/Nb Josephson junction consisting of a bottom NbSe 2 superconductor thin layer and a top Nb superconductor spaced by an atomically thin h -BN layer. We further characterized the superconducting current and voltage ( I – V ) relationships and Fraunhofer pattern of the NbSe 2 / h -BN/Nb junction. Notably, we demonstrated the critical current noise (1/ f noise power) in the h -BN-based Josephson device is at least a factor of four lower than that of the previously studied aluminum oxide-based Josephson junctions. Our work offers a strong promise of h -BN as a novel tunnel barrier for high-quality Josephson junctions and qubit applications.
We compute the decoherence caused by
1∕f fluctuations at low frequency
f in the critical current
I0 of Josephson junctions incorporated into flux, phase, charge, and hybrid flux-charge superconducting quantum bits (qubits). The dephasing time ${\ensuremath{\tau}}_{\ensuremath{\phi}}$ scales as ${I}_{0}∕\ensuremath{\Omega}\ensuremath{\Lambda}{S}_{{I}_{0}}^{1∕2}(1\phantom{\rule{0.3em}{0ex}}\mathrm{Hz})$, where $\ensuremath{\Omega}∕2\ensuremath{\pi}$ is the energy-level splitting frequency,
SI0(1Hz) is the spectral density of the critical-current noise at
1Hz, and $\ensuremath{\Lambda}\ensuremath{\equiv}\ensuremath{\mid}{I}_{0}d\ensuremath{\Omega}∕\ensuremath{\Omega}d{I}_{0}\ensuremath{\mid}$ is a parameter computed for given parameters for each type of qubit that specifies the sensitivity of the level splitting to critical-current fluctuations. Computer simulations show that the envelope of the coherent oscillations of any qubit after time
t scales as $\mathrm{exp}(\ensuremath{-}{t}^{2}∕2{\ensuremath{\tau}}_{\ensuremath{\phi}}^{2})$ when the dephasing due to critical-current noise dominates the dephasing from all sources of dissipation. We compile published results for fluctuations in the critical current of Josephson tunnel junctions fabricated with different technologies and a wide range in
I0 and area
A, and show that their values of
SI0(1Hz) scale to within a factor of 3 of $[144{({I}_{0}∕\ensuremath{\mu}\mathrm{A})}^{2}∕(\mathcal{A}∕\ensuremath{\mu}{\mathrm{m}}^{2})]{(\mathrm{pA})}^{2}∕\mathrm{Hz}$ at
4.2K. We empirically extrapolate
SI01∕2(1Hz) to lower temperatures using a scaling
T(K)∕4.2. Using this result, we find that the predicted values of ${\ensuremath{\tau}}_{\ensuremath{\phi}}$ at
100mK range from $0.8\phantom{\rule{0.5em}{0ex}}\text{to}\phantom{\rule{0.5em}{0ex}}12\phantom{\rule{0.3em}{0ex}}\ensuremath{\mu}\mathrm{s}$, and are usually substantially longer than values measured experimentally at lower temperatures.
Josephson junctions (JJs) are critical components in superconducting quantum circuits, where their electrical properties directly determine qubit transition frequencies. While advances in fabrication have enabled precise control over junction area and oxide thickness, the influence of junction geometry beyond area has remained largely unexplored. Here, we report clear and reproducible evidence that the normal-state resistance (Rn) of JJs depends strongly on geometric parameters, demonstrating that (Rn) exhibits a systematic and reproducible dependence on junction geometry beyond simple area scaling. To account for this behavior, we introduce an edge-resistance model that incorporates perimeter-related contributions to (Rn). Our findings highlight the crucial role of geometric design in JJ electrical characteristics and provide a practical framework for improving frequency precision and uniformity in large-scale superconducting quantum processors.